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common_source_project-fm7: Commit

Common Source Code Project for Qt (a.k.a for FM-7).

Commit MetaInfo

Revisão	6b3e6fc721c95cc9e7f8eb941f9139f711a2205e (tree)
Hora	2017-05-24 23:03:34
Autor	K.Ohta <whatisthis.sowhat@gmai...>
Commiter	K.Ohta

Mensagem de Log

[VM][COMMON_VM] Move I8237, I8253, I8255, I8259, UPD7220 and Z80SIO to common dll.

Mudança Sumário

modified: source/build-cmake/cmake/config_emufmr50.cmake (diff)
modified: source/build-cmake/cmake/config_emupc9801.cmake (diff)
modified: source/build-cmake/cmake/config_mz2500.cmake (diff)
modified: source/build-cmake/cmake/config_mz5500.cmake (diff)
modified: source/build-cmake/cmake/config_mz700.cmake (diff)
modified: source/build-cmake/cmake/config_pc8801.cmake (diff)
modified: source/build-cmake/cmake/config_pc98ha.cmake (diff)
modified: source/build-cmake/cmake/config_qc10.cmake (diff)
modified: source/build-cmake/cmake/config_tk80.cmake (diff)
modified: source/build-cmake/cmake/config_x1.cmake (diff)
modified: source/build-cmake/fm16pi/CMakeLists.txt (diff)
modified: source/build-cmake/fmr30_i286/CMakeLists.txt (diff)
modified: source/build-cmake/fmr30_i86/CMakeLists.txt (diff)
modified: source/build-cmake/hc20/CMakeLists.txt (diff)
modified: source/build-cmake/hc40/CMakeLists.txt (diff)
modified: source/build-cmake/hc80/CMakeLists.txt (diff)
modified: source/build-cmake/j3100gt/CMakeLists.txt (diff)
modified: source/build-cmake/j3100sl/CMakeLists.txt (diff)
modified: source/build-cmake/jx/CMakeLists.txt (diff)
modified: source/build-cmake/multi8/CMakeLists.txt (diff)
modified: source/build-cmake/mz2800/CMakeLists.txt (diff)
modified: source/build-cmake/mz3500/CMakeLists.txt (diff)
modified: source/build-cmake/n5200/CMakeLists.txt (diff)
modified: source/build-cmake/pc100/CMakeLists.txt (diff)
modified: source/src/vm/common_vm/CMakeLists.txt (diff)
modified: source/src/vm/fmr30/memory.cpp (diff)
modified: source/src/vm/fmr30/scsi.cpp (diff)
modified: source/src/vm/i8237.cpp (diff)
modified: source/src/vm/i8237.h (diff)
add: source/src/vm/i8237_base.cpp (diff)
modified: source/src/vm/i8253.cpp (diff)
modified: source/src/vm/i8253.h (diff)
modified: source/src/vm/i8255.cpp (diff)
modified: source/src/vm/i8255.h (diff)
modified: source/src/vm/i8259.cpp (diff)
modified: source/src/vm/i8259.h (diff)
modified: source/src/vm/j3100/dmareg.cpp (diff)
modified: source/src/vm/memory.h (diff)
modified: source/src/vm/n5200/floppy.cpp (diff)
modified: source/src/vm/n5200/system.cpp (diff)
modified: source/src/vm/upd7220.cpp (diff)
modified: source/src/vm/upd7220.h (diff)
add: source/src/vm/upd7220_base.cpp (diff)
modified: source/src/vm/z80sio.cpp (diff)
modified: source/src/vm/z80sio.h (diff)

Diff

--- a/source/build-cmake/cmake/config_emufmr50.cmake

+++ b/source/build-cmake/cmake/config_emufmr50.cmake

		@@ -13,10 +13,8 @@ set(WITH_MOUSE ON)
13	13
14	14	set(VMFILES
15	15	#
16		- i8253.cpp
17		- i8259.cpp
18		- msm58321.cpp
19	16	# mb8877.cpp
	17	+ msm58321.cpp
20	18	scsi_dev.cpp
21	19	scsi_host.cpp
22	20	scsi_hdd.cpp

		@@ -34,8 +32,12 @@ set(VMFILES_LIB
34	32	upd71071.cpp
35	33
36	34	i8251.cpp
	35	+ i8253.cpp
	36	+ i8259.cpp
	37	+ msm58321_base.cpp
	38	+
37	39	hd63484.cpp
38		- i386.cpp
	40	+# i386.cpp
39	41	disk.cpp
40	42	)
41	43

		@@ -97,7 +99,7 @@ elseif(BUILD_FMR60)
97	99	add_definitions(-DHAS_I286)
98	100	set(FLAG_USE_I386_VARIANTS OFF)
99	101	set(FLAG_USE_I286 ON)
100		- set(VMFILES ${VMFILES} hd63484.cpp)
	102	+ set(VMFILES_LIB ${VMFILES_LIB} hd63484.cpp)
101	103	set(RESOURCE ${CMAKE_SOURCE_DIR}/../../src/qt/common/qrc/fmr60.qrc)
102	104	elseif(BUILD_FMR70)
103	105	set(EXEC_TARGET emufmr70)

--- a/source/build-cmake/cmake/config_emupc9801.cmake

+++ b/source/build-cmake/cmake/config_emupc9801.cmake

		@@ -6,10 +6,6 @@ set(WITH_MOUSE ON)
6	6
7	7	set(VMFILES
8	8	i8237.cpp
9		- i8253.cpp
10		- i8255.cpp
11		- i8259.cpp
12		-
13	9	upd1990a.cpp
14	10	upd7220.cpp
15	11

		@@ -18,13 +14,18 @@ set(VMFILES
18	14	memory.cpp
19	15	)
20	16	set(VMFILES_LIB
	17	+ i8237_base.cpp
	18	+ i8251.cpp
	19	+ i8253.cpp
	20	+ i8255.cpp
	21	+ i8259.cpp
	22	+ ls244.cpp
21	23	pc80s31k.cpp
	24	+ upd7220_base.cpp
22	25	upd765a.cpp
23		- disk.cpp
24	26	ym2203.cpp
25		- i8251.cpp
26		- ls244.cpp
27	27	prnfile.cpp
	28	+ disk.cpp
28	29	)
29	30
30	31	set(BUILD_SHARED_LIBS OFF)

--- a/source/build-cmake/cmake/config_mz2500.cmake

+++ b/source/build-cmake/cmake/config_mz2500.cmake

		@@ -12,22 +12,18 @@ set(WITH_JOYSTICK ON)
12	12	set(WITH_MOUSE ON)
13	13	set(FLAG_USE_Z80 ON)
14	14	set(VMFILES_2500
15		- z80sio.cpp
16		-
17	15	w3100a.cpp
18	16	rp5c01.cpp
19	17
20	18	)
21	19	set(VMFILES_LIB_2500
	20	+ z80sio.cpp
22	21	ls393.cpp
23	22	ym2203.cpp
24	23	)
25	24
26	25	set(VMFILES_BASE
27	26	datarec.cpp
28		- i8253.cpp
29		- i8255.cpp
30		-
31	27	mz1p17.cpp
32	28
33	29	event.cpp

		@@ -36,6 +32,9 @@ set(VMFILES_BASE
36	32
37	33	)
38	34	set(VMFILES_LIB
	35	+ i8253.cpp
	36	+ i8255.cpp
	37	+
39	38	pcm1bit.cpp
40	39	z80pio.cpp
41	40	mb8877.cpp

		@@ -43,15 +42,18 @@ set(VMFILES_LIB
43	42	prnfile.cpp
44	43	)
45	44	set(VMFILES_QD
46		- z80sio.cpp
47	45	mz700/quickdisk.cpp
48		- )
	46	+)
	47	+set(VMFILES_LIB_QD
	48	+ z80sio.cpp
	49	+)
49	50
50	51	set(VMFILES_16BIT
51	52	i286.cpp
52		- i8259.cpp
53	53	)
54		-
	54	+set(VMFILES_LIB_16BIT
	55	+ i8259.cpp
	56	+)
55	57
56	58	set(BUILD_MZ2500 OFF CACHE BOOL "Build EMU-MZ2500")
57	59	set(BUILD_MZ2200 OFF CACHE BOOL "Build EMU-MZ2200")

		@@ -82,6 +84,7 @@ set(USE_FMGEN ON)
82	84
83	85	elseif(BUILD_MZ2000)
84	86	set(VMFILES ${VMFILES_BASE} ${VMFILES_QD} ${VMFILES_16BIT})
	87	+set(VMFILES_LIB ${VMFILES_LIB_BASE} ${VMFILES_LIB_QD} ${VMFILES_LIB_16BIT})
85	88	add_definitions(-D_MZ2000)
86	89	set(EXEC_TARGET emumz2000)
87	90	set(RESOURCE ${CMAKE_SOURCE_DIR}/../../src/qt/common/qrc/mz2000.qrc)

		@@ -89,6 +92,7 @@ set(USE_FMGEN OFF)
89	92
90	93	elseif(BUILD_MZ2200)
91	94	set(VMFILES ${VMFILES_BASE} ${VMFILES_QD} ${VMFILES_16BIT})
	95	+set(VMFILES_LIB ${VMFILES_LIB_BASE} ${VMFILES_LIB_QD} ${VMFILES_LIB_16BIT})
92	96	set(LOCAL_LIBS ${LOCAL_LIBS})
93	97	add_definitions(-D_MZ2200)
94	98	set(EXEC_TARGET emumz2200)

--- a/source/build-cmake/cmake/config_mz5500.cmake

+++ b/source/build-cmake/cmake/config_mz5500.cmake

		@@ -10,13 +10,10 @@ set(VMFILES
10	10	# i286.cpp
11	11
12	12	i8237.cpp
13		- i8255.cpp
14		- i8259.cpp
15	13	rp5c01.cpp
16	14
17	15	upd7220.cpp
18	16	z80ctc.cpp
19		- z80sio.cpp
20	17	mz1p17.cpp
21	18
22	19	event.cpp

		@@ -24,12 +21,19 @@ set(VMFILES
24	21	)
25	22
26	23	set(VMFILES_LIB
27		- prnfile.cpp
	24	+ i8237_base.cpp
	25	+ upd7220_base.cpp
	26	+ i8255.cpp
	27	+ i8259.cpp
28	28	ls393.cpp
29	29	not.cpp
	30	+
	31	+ prnfile.cpp
30	32	upd765a.cpp
31		- disk.cpp
32	33	ym2203.cpp
	34	+ z80sio.cpp
	35	+
	36	+ disk.cpp
33	37	)
34	38	set(BUILD_SHARED_LIBS OFF)
35	39	set(USE_OPENMP ON CACHE BOOL "Build using OpenMP")

--- a/source/build-cmake/cmake/config_mz700.cmake

+++ b/source/build-cmake/cmake/config_mz700.cmake

		@@ -11,9 +11,6 @@ set(WITH_MOUSE ON)
11	11
12	12	set(FLAG_USE_Z80 ON)
13	13	set(VMFILES_BASE
14		- i8255.cpp
15		- i8253.cpp
16		-
17	14	datarec.cpp
18	15
19	16	event.cpp

		@@ -22,7 +19,6 @@ set(VMFILES_BASE
22	19	)
23	20
24	21	set(VMFILES_MZ800 ${VMFILES_BASE}
25		- z80sio.cpp
26	22	)
27	23
28	24

		@@ -32,11 +28,15 @@ set(VMFILES_MZ1500 ${VMFILES_MZ800}
32	28	)
33	29
34	30	set(VMFILES_LIB
	31	+ i8255.cpp
	32	+ i8253.cpp
	33	+
35	34	beep.cpp
36	35	pcm1bit.cpp
37	36	and.cpp
38	37	)
39	38	set(VMFILES_LIB_MZ800
	39	+ z80sio.cpp
40	40	mb8877.cpp
41	41	disk.cpp
42	42	not.cpp

--- a/source/build-cmake/cmake/config_pc8801.cmake

+++ b/source/build-cmake/cmake/config_pc8801.cmake

		@@ -15,9 +15,6 @@ set(VMFILES
15	15
16	16
17	17	z80ctc.cpp
18		- z80sio.cpp
19		- i8255.cpp
20		-
21	18	datarec.cpp
22	19	event.cpp
23	20	io.cpp

		@@ -25,6 +22,8 @@ set(VMFILES
25	22	)
26	23	set(VMFILES_LIB
27	24	z80dma.cpp
	25	+ z80sio.cpp
	26	+
28	27	pc80s31k.cpp
29	28	upd765a.cpp
30	29	beep.cpp

		@@ -34,6 +33,7 @@ set(VMFILES_LIB
34	33	prnfile.cpp
35	34	ym2203.cpp
36	35	i8251.cpp
	36	+ i8255.cpp
37	37	)
38	38	set(FLAG_USE_Z80 ON)
39	39

--- a/source/build-cmake/cmake/config_pc98ha.cmake

+++ b/source/build-cmake/cmake/config_pc98ha.cmake

		@@ -5,20 +5,20 @@ set(WITH_JOYSTICK ON)
5	5	set(WITH_MOUSE ON)
6	6
7	7	set(VMFILES
8		- i8253.cpp
9		- i8259.cpp
10		- i8255.cpp
11		-
12	8	event.cpp
13	9	io.cpp
14	10	memory.cpp
15	11	)
16	12	set(VMFILES_LIB
17		- upd71071.cpp
18	13	beep.cpp
	14	+ i8251.cpp
	15	+ i8253.cpp
	16	+ i8255.cpp
	17	+ i8259.cpp
19	18	ls244.cpp
20	19	not.cpp
21		- i8251.cpp
	20	+
	21	+ upd71071.cpp
22	22	upd765a.cpp
23	23	disk.cpp
24	24	prnfile.cpp

--- a/source/build-cmake/cmake/config_qc10.cmake

+++ b/source/build-cmake/cmake/config_qc10.cmake

		@@ -5,24 +5,25 @@ set(WITH_MOUSE OFF)
5	5
6	6	set(FLAG_USE_Z80 ON)
7	7	set(VMFILES
8		- #
9		- z80sio.cpp
10		-
11	8	i8237.cpp
12		- i8253.cpp
13		- i8255.cpp
14		- i8259.cpp
15	9	upd7220.cpp
16		- upd765a.cpp
17	10
18	11	io.cpp
19	12
20		- disk.cpp
21	13	event.cpp
22	14	)
23	15	set(VMFILES_LIB
24		- hd146818p.cpp
25		- pcm1bit.cpp
	16	+ i8237_base.cpp
	17	+ i8253.cpp
	18	+ i8255.cpp
	19	+ i8259.cpp
	20	+ upd7220_base.cpp
	21	+ hd146818p.cpp
	22	+ pcm1bit.cpp
	23	+ upd765a.cpp
	24	+ z80sio.cpp
	25	+
	26	+ disk.cpp
26	27	)
27	28
28	29	set(BUILD_SHARED_LIBS OFF)

--- a/source/build-cmake/cmake/config_tk80.cmake

+++ b/source/build-cmake/cmake/config_tk80.cmake

		@@ -18,11 +18,11 @@ set(WITH_MOUSE ON)
18	18
19	19	set(VMFILES_BASE
20	20	i8080.cpp
21		- i8255.cpp
22	21	memory.cpp
23	22	event.cpp
24	23	)
25	24	set(VMFILES_LIB
	25	+ i8255.cpp
26	26	pcm1bit.cpp
27	27	)
28	28

--- a/source/build-cmake/cmake/config_x1.cmake

+++ b/source/build-cmake/cmake/config_x1.cmake

		@@ -13,14 +13,9 @@ set(USE_FMGEN ON)
13	13	set(WITH_JOYSTICK ON)
14	14	set(WITH_MOUSE ON)
15	15	set(VMFILES
16		-
17		-# hd46505.cpp
18		- i8255.cpp
19	16	upd1990a.cpp
20	17	z80ctc.cpp
21	18
22		- z80sio.cpp
23		-
24	19	datarec.cpp
25	20	event.cpp
26	21

		@@ -28,10 +23,13 @@ set(VMFILES
28	23	mz1p17.cpp
29	24	)
30	25	set(VMFILES_LIB
	26	+ z80sio.cpp
	27	+ z80pio.cpp
	28	+
	29	+ i8255.cpp
31	30	hd46505.cpp
32	31	mcs48.cpp
33	32	beep.cpp
34		- z80pio.cpp
35	33	ym2151.cpp
36	34	ym2203.cpp
37	35	ay_3_891x.cpp

--- a/source/build-cmake/fm16pi/CMakeLists.txt

+++ b/source/build-cmake/fm16pi/CMakeLists.txt

		@@ -22,14 +22,7 @@ set(WITH_MOUSE ON)
22	22
23	23	set(VMFILES
24	24	# i286.cpp
25		-#
26		- i8253.cpp
27		- i8255.cpp
28		- i8259.cpp
29	25	msm58321.cpp
30		-
31		- ym2203.cpp
32		-
33	26	# datarec.cpp
34	27	event.cpp
35	28	io.cpp

		@@ -37,6 +30,11 @@ set(VMFILES
37	30	)
38	31
39	32	set(VMFILES_LIB
	33	+ i8253.cpp
	34	+ i8255.cpp
	35	+ i8259.cpp
	36	+ ym2203.cpp
	37	+ msm58321_base.cpp
40	38	pcm1bit.cpp
41	39	i8251.cpp
42	40	not.cpp

--- a/source/build-cmake/fmr30_i286/CMakeLists.txt

+++ b/source/build-cmake/fmr30_i286/CMakeLists.txt

		@@ -16,10 +16,8 @@ project (emufmr30)
16	16	set(VM_NAME fmr30)
17	17	set(USE_FMGEN OFF)
18	18	set(VMFILES
19		-# i286.cpp
	19	+# i286.cpp
20	20	i8237.cpp
21		- i8253.cpp
22		- i8259.cpp
23	21	fmr50/bios.cpp
24	22
25	23	scsi_dev.cpp

		@@ -33,6 +31,9 @@ set(VMFILES
33	31	set(VMFILES_LIB
34	32	pcm1bit.cpp
35	33	i8251.cpp
	34	+ i8253.cpp
	35	+ i8259.cpp
	36	+ i8237_base.cpp
36	37	sn76489an.cpp
37	38	mb8877.cpp
38	39	disk.cpp

--- a/source/build-cmake/fmr30_i86/CMakeLists.txt

+++ b/source/build-cmake/fmr30_i86/CMakeLists.txt

		@@ -18,8 +18,6 @@ set(USE_FMGEN OFF)
18	18	set(VMFILES
19	19	# i286.cpp
20	20	i8237.cpp
21		- i8253.cpp
22		- i8259.cpp
23	21	fmr50/bios.cpp
24	22
25	23	scsi_dev.cpp

		@@ -33,6 +31,9 @@ set(VMFILES
33	31	set(VMFILES_LIB
34	32	pcm1bit.cpp
35	33	i8251.cpp
	34	+ i8253.cpp
	35	+ i8259.cpp
	36	+ i8237_base.cpp
36	37	sn76489an.cpp
37	38	mb8877.cpp
38	39	disk.cpp

--- a/source/build-cmake/hc20/CMakeLists.txt

+++ b/source/build-cmake/hc20/CMakeLists.txt

		@@ -20,25 +20,23 @@ set(VM_NAME hc20)
20	20	set(USE_FMGEN OFF)
21	21	set(WITH_JOYSTICK OFF)
22	22	set(WITH_MOUSE OFF)
	23	+set(FLAG_USE_Z80 ON)
23	24
24	25	set(VMFILES_BASE
25	26	mc6800.cpp
26		-# tf20.cpp
27		-
28		- z80.cpp
29		- z80sio.cpp
30		- i8255.cpp
31		-
32	27	datarec.cpp
33	28	event.cpp
34	29	io.cpp
35	30	memory.cpp
36	31	)
37	32	set(VMFILES_LIB
38		- upd765a.cpp
39		- hd146818p.cpp
40	33	beep.cpp
	34	+ i8255.cpp
	35	+ hd146818p.cpp
	36	+
41	37	tf20.cpp
	38	+ upd765a.cpp
	39	+ z80sio.cpp
42	40	disk.cpp
43	41	)
44	42

--- a/source/build-cmake/hc40/CMakeLists.txt

+++ b/source/build-cmake/hc40/CMakeLists.txt

		@@ -23,14 +23,14 @@ set(WITH_MOUSE OFF)
23	23
24	24	set(FLAG_USE_Z80 ON)
25	25	set(VMFILES_BASE
26		- ptf20.cpp
27		- disk.cpp
28		-
29	26	datarec.cpp
30	27	event.cpp
31	28	)
32	29	set(VMFILES_LIB
33	30	beep.cpp
	31	+ ptf20.cpp
	32	+ disk.cpp
	33	+
34	34	)
35	35	set(USE_OPENMP ON CACHE BOOL "Build using OpenMP")
36	36	set(USE_OPENGL ON CACHE BOOL "Build using OpenGL")

--- a/source/build-cmake/hc80/CMakeLists.txt

+++ b/source/build-cmake/hc80/CMakeLists.txt

		@@ -23,14 +23,13 @@ set(WITH_MOUSE OFF)
23	23
24	24	set(FLAG_USE_Z80 ON)
25	25	set(VMFILES_BASE
26		- ptf20.cpp
27		- disk.cpp
28		- i8251.cpp
29		-
30	26	event.cpp
31	27	)
32	28	set(VMFILES_LIB
33	29	beep.cpp
	30	+ i8251.cpp
	31	+ ptf20.cpp
	32	+ disk.cpp
34	33	)
35	34
36	35	set(USE_OPENMP ON CACHE BOOL "Build using OpenMP")

--- a/source/build-cmake/j3100gt/CMakeLists.txt

+++ b/source/build-cmake/j3100gt/CMakeLists.txt

		@@ -21,12 +21,13 @@ set(WITH_MOUSE ON)
21	21
22	22	set(VMFILES
23	23	i8237.cpp
24		- i8253.cpp
25		- i8259.cpp
26	24	io.cpp
27	25	event.cpp
28	26	)
29	27	set(VMFILES_LIB
	28	+ i8237_base.cpp
	29	+ i8253.cpp
	30	+ i8259.cpp
30	31	hd46505.cpp
31	32	pcm1bit.cpp
32	33	upd765a.cpp

--- a/source/build-cmake/j3100sl/CMakeLists.txt

+++ b/source/build-cmake/j3100sl/CMakeLists.txt

		@@ -21,14 +21,14 @@ set(WITH_MOUSE ON)
21	21
22	22	set(VMFILES
23	23	i8237.cpp
24		- i8253.cpp
25		- i8259.cpp
26		-
27	24	io.cpp
28	25	event.cpp
29	26	)
30	27
31	28	set(VMFILES_LIB
	29	+ i8237_base.cpp
	30	+ i8253.cpp
	31	+ i8259.cpp
32	32	hd46505.cpp
33	33	pcm1bit.cpp
34	34	upd765a.cpp

--- a/source/build-cmake/jx/CMakeLists.txt

+++ b/source/build-cmake/jx/CMakeLists.txt

		@@ -24,15 +24,16 @@ set(WITH_MOUSE ON)
24	24	set(VMFILES_BASE
25	25	# i86.cpp
26	26
27		- i8253.cpp
28		- i8255.cpp
29		- i8259.cpp
30	27	io.cpp
31	28	memory.cpp
32	29	event.cpp
33	30	)
34	31	set(VMFILES_LIB
35	32	i8251.cpp
	33	+ i8253.cpp
	34	+ i8255.cpp
	35	+ i8259.cpp
	36	+
36	37	hd46505.cpp
37	38	pcm1bit.cpp
38	39	not.cpp

--- a/source/build-cmake/multi8/CMakeLists.txt

+++ b/source/build-cmake/multi8/CMakeLists.txt

		@@ -17,23 +17,21 @@ set(USE_FMGEN ON)
17	17	set(EXEC_TARGET emumulti8)
18	18	set(FLAG_USE_Z80 ON)
19	19	set(VMFILES_BASE
20		-
21		- hd46505.cpp
22		- i8253.cpp
23		- i8255.cpp
24		- i8259.cpp
25		-
26	20	io.cpp
27	21	datarec.cpp
28	22
29	23	event.cpp
30	24	)
31	25	set(VMFILES_LIB
32		- ym2203.cpp
33		- i8251.cpp
34		- beep.cpp
35		- upd765a.cpp
36		- disk.cpp
	26	+ hd46505.cpp
	27	+ i8251.cpp
	28	+ i8253.cpp
	29	+ i8255.cpp
	30	+ i8259.cpp
	31	+ beep.cpp
	32	+ upd765a.cpp
	33	+ ym2203.cpp
	34	+ disk.cpp
37	35	)
38	36	set(USE_OPENMP ON CACHE BOOL "Build using OpenMP")
39	37	set(USE_OPENGL ON CACHE BOOL "Build using OpenGL")

--- a/source/build-cmake/mz2800/CMakeLists.txt

+++ b/source/build-cmake/mz2800/CMakeLists.txt

		@@ -19,27 +19,27 @@ set(WITH_JOYSTICK ON)
19	19	set(WITH_MOUSE ON)
20	20
21	21	set(VMFILES
22		- i8253.cpp
23		- i8255.cpp
24		- i8259.cpp
25	22	rp5c01.cpp
26	23
27		- z80sio.cpp
28	24	mz1p17.cpp
29	25
30	26	event.cpp
31	27	io.cpp
32	28	)
33	29	set(VMFILES_LIB
34		- z80pio.cpp
35		- prnfile.cpp
36		-# i286.cpp
37		- upd71071.cpp
38		- mb8877.cpp
39		- not.cpp
40		- pcm1bit.cpp
41		- ym2203.cpp
42		- disk.cpp
	30	+ i8253.cpp
	31	+ i8255.cpp
	32	+ i8259.cpp
	33	+ z80sio.cpp
	34	+ z80pio.cpp
	35	+ prnfile.cpp
	36	+ # i286.cpp
	37	+ upd71071.cpp
	38	+ mb8877.cpp
	39	+ not.cpp
	40	+ pcm1bit.cpp
	41	+ ym2203.cpp
	42	+ disk.cpp
43	43	)
44	44	set(FLAG_USE_I286 ON)
45	45

--- a/source/build-cmake/mz3500/CMakeLists.txt

+++ b/source/build-cmake/mz3500/CMakeLists.txt

		@@ -21,9 +21,6 @@ set(WITH_MOUSE ON)
21	21	set(VMFILES
22	22	# z80.cpp
23	23
24		- i8253.cpp
25		- i8255.cpp
26		-
27	24	upd1990a.cpp
28	25	upd7220.cpp
29	26

		@@ -33,10 +30,14 @@ set(VMFILES
33	30	)
34	31	set(VMFILES_LIB
35	32	i8251.cpp
	33	+ i8253.cpp
	34	+ i8255.cpp
	35	+
36	36	ls244.cpp
37	37	not.cpp
38	38	pcm1bit.cpp
39	39	upd765a.cpp
	40	+ upd7220_base.cpp
40	41
41	42	prnfile.cpp
42	43

--- a/source/build-cmake/n5200/CMakeLists.txt

+++ b/source/build-cmake/n5200/CMakeLists.txt

		@@ -23,11 +23,7 @@ set(WITH_MOUSE ON)
23	23
24	24	set(VMFILES_BASE
25	25	# i386.cpp
26		-
27	26	i8237.cpp
28		- i8253.cpp
29		- i8255.cpp
30		- i8259.cpp
31	27
32	28	upd1990a.cpp
33	29	upd7220.cpp

		@@ -37,7 +33,12 @@ set(VMFILES_BASE
37	33	)
38	34	set(VMFILES_LIB
39	35	beep.cpp
	36	+ i8237_base.cpp
40	37	i8251.cpp
	38	+ i8253.cpp
	39	+ i8255.cpp
	40	+ i8259.cpp
	41	+ upd7220_base.cpp
41	42	upd765a.cpp
42	43	disk.cpp
43	44	)

--- a/source/build-cmake/pc100/CMakeLists.txt

+++ b/source/build-cmake/pc100/CMakeLists.txt

		@@ -20,10 +20,6 @@ set(WITH_MOUSE ON)
20	20
21	21	set(VMFILES
22	22	# i286.cpp
23		-
24		- i8255.cpp
25		- i8259.cpp
26		-
27	23	msm58321.cpp
28	24
29	25	memory.cpp

		@@ -31,9 +27,13 @@ set(VMFILES
31	27	io.cpp
32	28	)
33	29	set(VMFILES_LIB
	30	+ beep.cpp
34	31	and.cpp
35	32	i8251.cpp
36		- beep.cpp
	33	+ i8255.cpp
	34	+ i8259.cpp
	35	+ msm58321_base.cpp
	36	+
37	37	pcm1bit.cpp
38	38	upd765a.cpp
39	39	disk.cpp

--- a/source/src/vm/common_vm/CMakeLists.txt

+++ b/source/src/vm/common_vm/CMakeLists.txt

		@@ -19,11 +19,11 @@ set(s_vm_common_vm_srcs
19	19	# ../i8080.cpp
20	20
21	21	../i8155.cpp
22		-# ../i8237.cpp
	22	+ ../i8237_base.cpp
23	23	../i8251.cpp
24		-# ../i8253.cpp
25		-# ../i8255.cpp
26		-# ../i8259.cpp
	24	+ ../i8253.cpp
	25	+ ../i8255.cpp
	26	+ ../i8259.cpp
27	27	# ../i86.cpp
28	28	# ../io.cpp
29	29	# ../ld700.cpp

		@@ -71,7 +71,7 @@ set(s_vm_common_vm_srcs
71	71	# ../upd1990a.cpp
72	72	../upd4991a.cpp
73	73	../upd71071.cpp
74		-# ../upd7220.cpp
	74	+ ../upd7220_base.cpp
75	75	../upd765a.cpp
76	76	../upd7752.cpp
77	77	# ../upd7801.cpp

		@@ -87,7 +87,7 @@ set(s_vm_common_vm_srcs
87	87	# ../z80ctc.cpp
88	88	../z80dma.cpp
89	89	../z80pio.cpp
90		-# ../z80sio.cpp
	90	+ ../z80sio.cpp
91	91
92	92
93	93	../libcpu_newdev/mcs48_base.cpp

		@@ -120,8 +120,8 @@ else()
120	120	${s_vm_common_vm_srcs}
121	121	)
122	122	set_target_properties(CSPcommon_vm PROPERTIES
123		- SOVERSION 1.1.6
124		- VERSION 1.1.6
	123	+ SOVERSION 1.1.7
	124	+ VERSION 1.1.7
125	125	)
126	126	INSTALL(TARGETS CSPcommon_vm DESTINATION ${LIBCSP_INSTALL_DIR})
127	127	endif()

--- a/source/src/vm/fmr30/memory.cpp

+++ b/source/src/vm/fmr30/memory.cpp

		@@ -7,6 +7,8 @@
7	7	[ memory and crtc ]
8	8	*/
9	9
	10	+#include "../vm.h"
	11	+#include "../../emu.h"
10	12	#include "memory.h"
11	13	#include "../i8237.h"
12	14	#include "../i286.h"

--- a/source/src/vm/fmr30/scsi.cpp

+++ b/source/src/vm/fmr30/scsi.cpp

		@@ -7,6 +7,8 @@
7	7	[ scsi ]
8	8	*/
9	9
	10	+#include "../vm.h"
	11	+#include "../../emu.h"
10	12	#include "scsi.h"
11	13	#include "../i8237.h"
12	14	#include "../i8259.h"

--- a/source/src/vm/i8237.cpp

+++ b/source/src/vm/i8237.cpp

		@@ -8,13 +8,23 @@
8	8	[ i8237 ]
9	9	*/
10	10
	11	+#include "vm.h"
	12	+#include "../emu.h"
11	13	#include "i8237.h"
12	14
13		-void I8237::reset()
	15	+
	16	+I8237::I8237(VM* parent_vm, EMU* parent_emu) : I8237_BASE(parent_vm, parent_emu)
	17	+{
	18	+ for(int i = 0; i < 4; i++) {
	19	+ dma[i].dev = vm->dummy;
	20	+ }
	21	+#ifdef SINGLE_MODE_DMA
	22	+ d_dma = NULL;
	23	+#endif
	24	+}
	25	+
	26	+I8237::~I8237()
14	27	{
15		- low_high = false;
16		- cmd = req = tc = 0;
17		- mask = 0xff;
18	28	}
19	29
20	30	void I8237::write_io8(uint32_t addr, uint32_t data)

		@@ -88,40 +98,6 @@ void I8237::write_io8(uint32_t addr, uint32_t data)
88	98	}
89	99	}
90	100
91		-uint32_t I8237::read_io8(uint32_t addr)
92		-{
93		- int ch = (addr >> 1) & 3;
94		- uint32_t val = 0xff;
95		-
96		- switch(addr & 0x0f) {
97		- case 0x00: case 0x02: case 0x04: case 0x06:
98		- if(low_high) {
99		- val = dma[ch].areg >> 8;
100		- } else {
101		- val = dma[ch].areg & 0xff;
102		- }
103		- low_high = !low_high;
104		- return val;
105		- case 0x01: case 0x03: case 0x05: case 0x07:
106		- if(low_high) {
107		- val = dma[ch].creg >> 8;
108		- } else {
109		- val = dma[ch].creg & 0xff;
110		- }
111		- low_high = !low_high;
112		- return val;
113		- case 0x08:
114		- // status register
115		- val = (req << 4) \| tc;
116		- tc = 0;
117		- return val;
118		- case 0x0d:
119		- // temporary register
120		- return tmp & 0xff;
121		- }
122		- return 0xff;
123		-}
124		-
125	101	void I8237::write_signal(int id, uint32_t data, uint32_t mask)
126	102	{
127	103	if(SIG_I8237_CH0 <= id && id <= SIG_I8237_CH3) {

		@@ -207,42 +183,6 @@ void I8237::do_dma()
207	183	#endif
208	184	}
209	185
210		-void I8237::write_mem(uint32_t addr, uint32_t data)
211		-{
212		- if(mode_word) {
213		- d_mem->write_dma_data16(addr << 1, data);
214		- } else {
215		- d_mem->write_dma_data8(addr, data);
216		- }
217		-}
218		-
219		-uint32_t I8237::read_mem(uint32_t addr)
220		-{
221		- if(mode_word) {
222		- return d_mem->read_dma_data16(addr << 1);
223		- } else {
224		- return d_mem->read_dma_data8(addr);
225		- }
226		-}
227		-
228		-void I8237::write_io(int ch, uint32_t data)
229		-{
230		- if(mode_word) {
231		- dma[ch].dev->write_dma_io16(0, data);
232		- } else {
233		- dma[ch].dev->write_dma_io8(0, data);
234		- }
235		-}
236		-
237		-uint32_t I8237::read_io(int ch)
238		-{
239		- if(mode_word) {
240		- return dma[ch].dev->read_dma_io16(0);
241		- } else {
242		- return dma[ch].dev->read_dma_io8(0);
243		- }
244		-}
245		-
246	186	#define STATE_VERSION 1
247	187
248	188	void I8237::save_state(FILEIO* state_fio)

--- a/source/src/vm/i8237.h

+++ b/source/src/vm/i8237.h

		@@ -11,8 +11,8 @@
11	11	#ifndef _I8237_H_
12	12	#define _I8237_H_
13	13
14		-#include "vm.h"
15		-#include "../emu.h"
	14	+//#include "vm.h"
	15	+//#include "../emu.h"
16	16	#include "device.h"
17	17
18	18	#define SIG_I8237_CH0 0

		@@ -28,13 +28,11 @@
28	28	#define SIG_I8237_MASK2 10
29	29	#define SIG_I8237_MASK3 11
30	30
31		-class I8237 : public DEVICE
	31	+
	32	+class I8237_BASE : public DEVICE
32	33	{
33		-private:
	34	+protected:
34	35	DEVICE* d_mem;
35		-#ifdef SINGLE_MODE_DMA
36		- DEVICE* d_dma;
37		-#endif
38	36
39	37	struct {
40	38	DEVICE* dev;

		@@ -57,36 +55,35 @@ private:
57	55	uint8_t tc;
58	56	uint32_t tmp;
59	57	bool mode_word;
60		-
	58	+
61	59	void write_mem(uint32_t addr, uint32_t data);
62	60	uint32_t read_mem(uint32_t addr);
63	61	void write_io(int ch, uint32_t data);
64	62	uint32_t read_io(int ch);
65	63
66	64	public:
67		- I8237(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
	65	+ I8237_BASE(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
68	66	{
69	67	for(int i = 0; i < 4; i++) {
70		- dma[i].dev = vm->dummy;
	68	+ //dma[i].dev = vm->dummy;
	69	+ dma[i].dev = NULL;
71	70	dma[i].bankreg = dma[i].incmask = 0;
72	71	initialize_output_signals(&dma[i].outputs_tc);
73	72	}
74		-#ifdef SINGLE_MODE_DMA
75		- d_dma = NULL;
76		-#endif
77	73	mode_word = false;
78	74	set_device_name(_T("i8237 DMAC"));
79	75	}
80		- ~I8237() {}
	76	+ ~I8237_BASE() {}
81	77
82	78	// common functions
	79	+ void initialize();
83	80	void reset();
84		- void write_io8(uint32_t addr, uint32_t data);
	81	+ virtual void write_io8(uint32_t addr, uint32_t data);
85	82	uint32_t read_io8(uint32_t addr);
86		- void write_signal(int id, uint32_t data, uint32_t mask);
87		- void do_dma();
88		- void save_state(FILEIO* state_fio);
89		- bool load_state(FILEIO* state_fio);
	83	+ virtual void write_signal(int id, uint32_t data, uint32_t mask);
	84	+ virtual void do_dma();
	85	+ virtual void save_state(FILEIO* state_fio) {};
	86	+ virtual bool load_state(FILEIO* state_fio) { return false;}
90	87
91	88	// unique functions
92	89	void set_context_memory(DEVICE* device)

		@@ -125,16 +122,32 @@ public:
125	122	{
126	123	register_output_signal(&dma[0].outputs_tc, device, id, mask);
127	124	}
	125	+ void set_mode_word(bool val)
	126	+ {
	127	+ mode_word = val;
	128	+ }
	129	+};
	130	+
	131	+class I8237 : public I8237_BASE {
	132	+private:
	133	+#ifdef SINGLE_MODE_DMA
	134	+ DEVICE* d_dma;
	135	+#endif
	136	+public:
	137	+ I8237(VM* parent_vm, EMU* parent_emu);
	138	+ ~I8237();
	139	+
	140	+ virtual void write_io8(uint32_t addr, uint32_t data);
	141	+ void write_signal(int id, uint32_t data, uint32_t mask);
	142	+ void do_dma();
	143	+ void save_state(FILEIO* state_fio);
	144	+ bool load_state(FILEIO* state_fio);
128	145	#ifdef SINGLE_MODE_DMA
129	146	void set_context_child_dma(DEVICE* device)
130	147	{
131	148	d_dma = device;
132	149	}
133	150	#endif
134		- void set_mode_word(bool val)
135		- {
136		- mode_word = val;
137		- }
138	151	};
139	152
140	153	#endif

--- /dev/null

+++ b/source/src/vm/i8237_base.cpp

		@@ -0,0 +1,111 @@
	1	+/*
	2	+ Skelton for retropc emulator
	3	+
	4	+ Origin : MESS
	5	+ Author : Takeda.Toshiya
	6	+ Date : 2006.12.06 -
	7	+
	8	+ [ i8237 ]
	9	+*/
	10	+
	11	+#include "i8237.h"
	12	+
	13	+void I8237_BASE::initialize()
	14	+{
	15	+ DEVICE::initialize();
	16	+}
	17	+
	18	+void I8237_BASE::reset()
	19	+{
	20	+ low_high = false;
	21	+ cmd = req = tc = 0;
	22	+ mask = 0xff;
	23	+}
	24	+
	25	+void I8237_BASE::write_io8(uint32_t addr, uint32_t data)
	26	+{
	27	+ // Dummy function
	28	+}
	29	+
	30	+uint32_t I8237_BASE::read_io8(uint32_t addr)
	31	+{
	32	+ int ch = (addr >> 1) & 3;
	33	+ uint32_t val = 0xff;
	34	+
	35	+ switch(addr & 0x0f) {
	36	+ case 0x00: case 0x02: case 0x04: case 0x06:
	37	+ if(low_high) {
	38	+ val = dma[ch].areg >> 8;
	39	+ } else {
	40	+ val = dma[ch].areg & 0xff;
	41	+ }
	42	+ low_high = !low_high;
	43	+ return val;
	44	+ case 0x01: case 0x03: case 0x05: case 0x07:
	45	+ if(low_high) {
	46	+ val = dma[ch].creg >> 8;
	47	+ } else {
	48	+ val = dma[ch].creg & 0xff;
	49	+ }
	50	+ low_high = !low_high;
	51	+ return val;
	52	+ case 0x08:
	53	+ // status register
	54	+ val = (req << 4) \| tc;
	55	+ tc = 0;
	56	+ return val;
	57	+ case 0x0d:
	58	+ // temporary register
	59	+ return tmp & 0xff;
	60	+ }
	61	+ return 0xff;
	62	+}
	63	+
	64	+void I8237_BASE::write_signal(int id, uint32_t data, uint32_t mask)
	65	+{
	66	+ // Dummy function
	67	+}
	68	+
	69	+// note: if SINGLE_MODE_DMA is defined, do_dma() is called in every machine cycle
	70	+
	71	+void I8237_BASE::do_dma()
	72	+{
	73	+ // Dummy function
	74	+}
	75	+
	76	+void I8237_BASE::write_mem(uint32_t addr, uint32_t data)
	77	+{
	78	+ if(mode_word) {
	79	+ d_mem->write_dma_data16(addr << 1, data);
	80	+ } else {
	81	+ d_mem->write_dma_data8(addr, data);
	82	+ }
	83	+}
	84	+
	85	+uint32_t I8237_BASE::read_mem(uint32_t addr)
	86	+{
	87	+ if(mode_word) {
	88	+ return d_mem->read_dma_data16(addr << 1);
	89	+ } else {
	90	+ return d_mem->read_dma_data8(addr);
	91	+ }
	92	+}
	93	+
	94	+void I8237_BASE::write_io(int ch, uint32_t data)
	95	+{
	96	+ if(mode_word) {
	97	+ dma[ch].dev->write_dma_io16(0, data);
	98	+ } else {
	99	+ dma[ch].dev->write_dma_io8(0, data);
	100	+ }
	101	+}
	102	+
	103	+uint32_t I8237_BASE::read_io(int ch)
	104	+{
	105	+ if(mode_word) {
	106	+ return dma[ch].dev->read_dma_io16(0);
	107	+ } else {
	108	+ return dma[ch].dev->read_dma_io8(0);
	109	+ }
	110	+}
	111	+

--- a/source/src/vm/i8253.cpp

+++ b/source/src/vm/i8253.cpp

		@@ -12,6 +12,7 @@
12	12	void I8253::initialize()
13	13	{
14	14	DEVICE::initialize();
	15	+ __HAS_I8254 = osd->check_feature(_T("HAS_I8254"));
15	16	for(int ch = 0; ch < 3; ch++) {
16	17	counter[ch].prev_out = true;
17	18	counter[ch].prev_in = false;

		@@ -25,11 +26,16 @@ void I8253::initialize()
25	26	counter[ch].low_write = counter[ch].high_write = false;
26	27	counter[ch].delay = false;
27	28	counter[ch].start = false;
28		-#ifdef HAS_I8254
29		- // 8254 read-back command
30		- counter[ch].null_count = true;
31		- counter[ch].status_latched = false;
32		-#endif
	29	+//#ifdef HAS_I8254
	30	+ if(__HAS_I8254) {
	31	+ // 8254 read-back command
	32	+ counter[ch].null_count = true;
	33	+ counter[ch].status_latched = false;
	34	+ } else {
	35	+ counter[ch].null_count = false;
	36	+ counter[ch].status_latched = false;
	37	+ }
	38	+//#endif
33	39	}
34	40	}
35	41

		@@ -70,9 +76,9 @@ void I8253::write_io8(uint32_t addr, uint32_t data)
70	76	}
71	77	counter[ch].high_write = false;
72	78	}
73		-#ifdef HAS_I8254
74		- counter[ch].null_count = true;
75		-#endif
	79	+//#ifdef HAS_I8254
	80	+ if(__HAS_I8254) counter[ch].null_count = true;
	81	+//#endif
76	82	// set signal
77	83	if(counter[ch].mode == 0) {
78	84	set_signal(ch, false);

		@@ -96,7 +102,8 @@ void I8253::write_io8(uint32_t addr, uint32_t data)
96	102
97	103	case 3: // ctrl reg
98	104	if((data & 0xc0) == 0xc0) {
99		-#ifdef HAS_I8254
	105	+//#ifdef HAS_I8254
	106	+ if(!__HAS_I8254) break;
100	107	// i8254 read-back command
101	108	for(ch = 0; ch < 3; ch++) {
102	109	uint8_t bit = 2 << ch;

		@@ -114,7 +121,7 @@ void I8253::write_io8(uint32_t addr, uint32_t data)
114	121	latch_count(ch);
115	122	}
116	123	}
117		-#endif
	124	+//#endif
118	125	break;
119	126	}
120	127	ch = (data >> 6) & 3;

		@@ -138,9 +145,9 @@ void I8253::write_io8(uint32_t addr, uint32_t data)
138	145	stop_count(ch);
139	146	counter[ch].count_reg = 0;
140	147	// }
141		-#ifdef HAS_I8254
142		- counter[ch].null_count = true;
143		-#endif
	148	+//#ifdef HAS_I8254
	149	+ if(__HAS_I8254) counter[ch].null_count = true;
	150	+//#endif
144	151	} else if(!counter[ch].count_latched) {
145	152	latch_count(ch);
146	153	}

		@@ -156,12 +163,12 @@ uint32_t I8253::read_io8(uint32_t addr)
156	163	case 0:
157	164	case 1:
158	165	case 2:
159		-#ifdef HAS_I8254
160		- if(counter[ch].status_latched) {
	166	+//#ifdef HAS_I8254
	167	+ if((__HAS_I8254) && (counter[ch].status_latched)) {
161	168	counter[ch].status_latched = false;
162	169	return counter[ch].status;
163	170	}
164		-#endif
	171	+//#endif
165	172	// if not latched, through current count
166	173	if(!counter[ch].count_latched) {
167	174	if(!counter[ch].low_read && !counter[ch].high_read) {

		@@ -243,9 +250,9 @@ void I8253::input_clock(int ch, int clock)
243	250	clock -= 1;
244	251	counter[ch].delay = false;
245	252	counter[ch].count = COUNT_VALUE(ch);
246		-#ifdef HAS_I8254
247		- counter[ch].null_count = false;
248		-#endif
	253	+//#ifdef HAS_I8254
	254	+ if(__HAS_I8254) counter[ch].null_count = false;
	255	+//#endif
249	256	}
250	257
251	258	// update counter

		@@ -268,9 +275,9 @@ loop:
268	275	if(counter[ch].count <= 0) {
269	276	if(counter[ch].mode == 0 \|\| counter[ch].mode == 2 \|\| counter[ch].mode == 3) {
270	277	counter[ch].count += tmp;
271		-#ifdef HAS_I8254
272		- counter[ch].null_count = false;
273		-#endif
	278	+//#ifdef HAS_I8254
	279	+ if(__HAS_I8254) counter[ch].null_count = false;
	280	+//#endif
274	281	goto loop;
275	282	} else {
276	283	counter[ch].start = false;

		@@ -430,11 +437,13 @@ void I8253::save_state(FILEIO* state_fio)
430	437	state_fio->FputInt32(counter[i].mode);
431	438	state_fio->FputBool(counter[i].delay);
432	439	state_fio->FputBool(counter[i].start);
433		-#ifdef HAS_I8254
434		- state_fio->FputBool(counter[i].null_count);
435		- state_fio->FputBool(counter[i].status_latched);
436		- state_fio->FputUint8(counter[i].status);
437		-#endif
	440	+//#ifdef HAS_I8254
	441	+ if(__HAS_I8254) {
	442	+ state_fio->FputBool(counter[i].null_count);
	443	+ state_fio->FputBool(counter[i].status_latched);
	444	+ state_fio->FputUint8(counter[i].status);
	445	+ }
	446	+//#endif
438	447	state_fio->FputUint64(counter[i].freq);
439	448	state_fio->FputInt32(counter[i].register_id);
440	449	state_fio->FputUint32(counter[i].input_clk);

		@@ -468,11 +477,13 @@ bool I8253::load_state(FILEIO* state_fio)
468	477	counter[i].mode = state_fio->FgetInt32();
469	478	counter[i].delay = state_fio->FgetBool();
470	479	counter[i].start = state_fio->FgetBool();
471		-#ifdef HAS_I8254
472		- counter[i].null_count = state_fio->FgetBool();
473		- counter[i].status_latched = state_fio->FgetBool();
474		- counter[i].status = state_fio->FgetUint8();
475		-#endif
	480	+//#ifdef HAS_I8254
	481	+ if(__HAS_I8254) {
	482	+ counter[i].null_count = state_fio->FgetBool();
	483	+ counter[i].status_latched = state_fio->FgetBool();
	484	+ counter[i].status = state_fio->FgetUint8();
	485	+ }
	486	+//#endif
476	487	counter[i].freq = state_fio->FgetUint64();
477	488	counter[i].register_id = state_fio->FgetInt32();
478	489	counter[i].input_clk = state_fio->FgetUint32();

--- a/source/src/vm/i8253.h

+++ b/source/src/vm/i8253.h

		@@ -10,8 +10,8 @@
10	10	#ifndef _I8253_H_
11	11	#define _I8253_H_
12	12
13		-#include "vm.h"
14		-#include "../emu.h"
	13	+//#include "vm.h"
	14	+//#include "../emu.h"
15	15	#include "device.h"
16	16
17	17	#define SIG_I8253_CLOCK_0 0

		@@ -38,11 +38,11 @@ private:
38	38	int mode;
39	39	bool delay;
40	40	bool start;
41		-#ifdef HAS_I8254
	41	+//#ifdef HAS_I8254
42	42	bool null_count;
43	43	bool status_latched;
44	44	uint8_t status;
45		-#endif
	45	+//#endif
46	46	// constant clock
47	47	uint64_t freq;
48	48	int register_id;

		@@ -53,6 +53,8 @@ private:
53	53	outputs_t outputs;
54	54	} counter[3];
55	55	uint64_t cpu_clocks;
	56	+
	57	+ bool __HAS_I8254;
56	58
57	59	void input_clock(int ch, int clock);
58	60	void input_gate(int ch, bool signal);

--- a/source/src/vm/i8255.cpp

+++ b/source/src/vm/i8255.cpp

		@@ -23,6 +23,12 @@
23	23	#define BIT_INTR_A 0x08 // PC3
24	24	#define BIT_INTR_B 0x01 // PC0
25	25
	26	+void I8255::initialize()
	27	+{
	28	+ DEVICE::initialize();
	29	+ __I8255_AUTO_HAND_SHAKE = osd->check_feature(_T("I8255_AUTO_HAND_SHAKE"));
	30	+}
	31	+
26	32	void I8255::reset()
27	33	{
28	34	for(int i = 0; i < 3; i++) {

		@@ -44,7 +50,8 @@ void I8255::write_io8(uint32_t addr, uint32_t data)
44	50	write_signals(&port[ch].outputs, port[ch].wreg = data);
45	51	port[ch].first = false;
46	52	}
47		-#ifndef I8255_AUTO_HAND_SHAKE
	53	+//#ifndef I8255_AUTO_HAND_SHAKE
	54	+ if(__I8255_AUTO_HAND_SHAKE) break;
48	55	if(ch == 0) {
49	56	if(port[0].mode == 1 \|\| port[0].mode == 2) {
50	57	uint32_t val = port[2].wreg & ~BIT_OBF_A;

		@@ -62,7 +69,7 @@ void I8255::write_io8(uint32_t addr, uint32_t data)
62	69	write_io8(2, val);
63	70	}
64	71	}
65		-#endif
	72	+//#endif
66	73	break;
67	74	case 3:
68	75	if(data & 0x80) {

		@@ -144,7 +151,8 @@ void I8255::write_signal(int id, uint32_t data, uint32_t mask)
144	151	switch(id) {
145	152	case SIG_I8255_PORT_A:
146	153	port[0].rreg = (port[0].rreg & ~mask) \| (data & mask);
147		-#ifdef I8255_AUTO_HAND_SHAKE
	154	+//#ifdef I8255_AUTO_HAND_SHAKE
	155	+ if(!__I8255_AUTO_HAND_SHAKE) break;
148	156	if(port[0].mode == 1 \|\| port[0].mode == 2) {
149	157	uint32_t val = port[2].wreg \| BIT_IBF_A;
150	158	if(port[2].wreg & BIT_STB_A) {

		@@ -152,11 +160,12 @@ void I8255::write_signal(int id, uint32_t data, uint32_t mask)
152	160	}
153	161	write_io8(2, val);
154	162	}
155		-#endif
	163	+//#endif
156	164	break;
157	165	case SIG_I8255_PORT_B:
158	166	port[1].rreg = (port[1].rreg & ~mask) \| (data & mask);
159		-#ifdef I8255_AUTO_HAND_SHAKE
	167	+//#ifdef I8255_AUTO_HAND_SHAKE
	168	+ if(!__I8255_AUTO_HAND_SHAKE) break;
160	169	if(port[1].mode == 1) {
161	170	uint32_t val = port[2].wreg \| BIT_IBF_B;
162	171	if(port[2].wreg & BIT_STB_B) {

		@@ -164,54 +173,56 @@ void I8255::write_signal(int id, uint32_t data, uint32_t mask)
164	173	}
165	174	write_io8(2, val);
166	175	}
167		-#endif
	176	+//#endif
168	177	break;
169	178	case SIG_I8255_PORT_C:
170		-#ifndef I8255_AUTO_HAND_SHAKE
171		- if(port[0].mode == 1 \|\| port[0].mode == 2) {
172		- if(mask & BIT_STB_A) {
173		- if((port[2].rreg & BIT_STB_A) && !(data & BIT_STB_A)) {
174		- write_io8(2, port[2].wreg \| BIT_IBF_A);
175		- } else if(!(port[2].rreg & BIT_STB_A) && (data & BIT_STB_A)) {
176		- if(port[2].wreg & BIT_STB_A) {
177		- write_io8(2, port[2].wreg \| BIT_INTR_A);
	179	+//#ifndef I8255_AUTO_HAND_SHAKE
	180	+ if(!__I8255_AUTO_HAND_SHAKE) {
	181	+ if(port[0].mode == 1 \|\| port[0].mode == 2) {
	182	+ if(mask & BIT_STB_A) {
	183	+ if((port[2].rreg & BIT_STB_A) && !(data & BIT_STB_A)) {
	184	+ write_io8(2, port[2].wreg \| BIT_IBF_A);
	185	+ } else if(!(port[2].rreg & BIT_STB_A) && (data & BIT_STB_A)) {
	186	+ if(port[2].wreg & BIT_STB_A) {
	187	+ write_io8(2, port[2].wreg \| BIT_INTR_A);
	188	+ }
178	189	}
179	190	}
180		- }
181		- if(mask & BIT_ACK_A) {
182		- if((port[2].rreg & BIT_ACK_A) && !(data & BIT_ACK_A)) {
183		- write_io8(2, port[2].wreg \| BIT_OBF_A);
184		- } else if(!(port[2].rreg & BIT_ACK_A) && (data & BIT_ACK_A)) {
185		- if(port[2].wreg & BIT_ACK_A) {
186		- write_io8(2, port[2].wreg \| BIT_INTR_A);
	191	+ if(mask & BIT_ACK_A) {
	192	+ if((port[2].rreg & BIT_ACK_A) && !(data & BIT_ACK_A)) {
	193	+ write_io8(2, port[2].wreg \| BIT_OBF_A);
	194	+ } else if(!(port[2].rreg & BIT_ACK_A) && (data & BIT_ACK_A)) {
	195	+ if(port[2].wreg & BIT_ACK_A) {
	196	+ write_io8(2, port[2].wreg \| BIT_INTR_A);
	197	+ }
187	198	}
188	199	}
189	200	}
190		- }
191		- if(port[1].mode == 1) {
192		- if(port[0].rmask == 0xff) {
193		- if(mask & BIT_STB_B) {
194		- if((port[2].rreg & BIT_STB_B) && !(data & BIT_STB_B)) {
195		- write_io8(2, port[2].wreg \| BIT_IBF_B);
196		- } else if(!(port[2].rreg & BIT_STB_B) && (data & BIT_STB_B)) {
197		- if(port[2].wreg & BIT_STB_B) {
198		- write_io8(2, port[2].wreg \| BIT_INTR_B);
	201	+ if(port[1].mode == 1) {
	202	+ if(port[0].rmask == 0xff) {
	203	+ if(mask & BIT_STB_B) {
	204	+ if((port[2].rreg & BIT_STB_B) && !(data & BIT_STB_B)) {
	205	+ write_io8(2, port[2].wreg \| BIT_IBF_B);
	206	+ } else if(!(port[2].rreg & BIT_STB_B) && (data & BIT_STB_B)) {
	207	+ if(port[2].wreg & BIT_STB_B) {
	208	+ write_io8(2, port[2].wreg \| BIT_INTR_B);
	209	+ }
199	210	}
200	211	}
201		- }
202		- } else {
203		- if(mask & BIT_ACK_B) {
204		- if((port[2].rreg & BIT_ACK_B) && !(data & BIT_ACK_B)) {
205		- write_io8(2, port[2].wreg \| BIT_OBF_B);
206		- } else if(!(port[2].rreg & BIT_ACK_B) && (data & BIT_ACK_B)) {
207		- if(port[2].wreg & BIT_ACK_B) {
208		- write_io8(2, port[2].wreg \| BIT_INTR_B);
	212	+ } else {
	213	+ if(mask & BIT_ACK_B) {
	214	+ if((port[2].rreg & BIT_ACK_B) && !(data & BIT_ACK_B)) {
	215	+ write_io8(2, port[2].wreg \| BIT_OBF_B);
	216	+ } else if(!(port[2].rreg & BIT_ACK_B) && (data & BIT_ACK_B)) {
	217	+ if(port[2].wreg & BIT_ACK_B) {
	218	+ write_io8(2, port[2].wreg \| BIT_INTR_B);
	219	+ }
209	220	}
210	221	}
211	222	}
212	223	}
213	224	}
214		-#endif
	225	+//#endif
215	226	port[2].rreg = (port[2].rreg & ~mask) \| (data & mask);
216	227	break;
217	228	}

--- a/source/src/vm/i8255.h

+++ b/source/src/vm/i8255.h

		@@ -10,8 +10,8 @@
10	10	#ifndef _I8255_H_
11	11	#define _I8255_H_
12	12
13		-#include "vm.h"
14		-#include "../emu.h"
	13	+//#include "vm.h"
	14	+//#include "../emu.h"
15	15	#include "device.h"
16	16
17	17	#define SIG_I8255_PORT_A 0

		@@ -30,6 +30,7 @@ private:
30	30	// output signals
31	31	outputs_t outputs;
32	32	} port[3];
	33	+ bool __I8255_AUTO_HAND_SHAKE;
33	34
34	35	public:
35	36	I8255(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)

		@@ -39,11 +40,13 @@ public:
39	40	port[i].wreg = port[i].rreg = 0;//0xff;
40	41	}
41	42	clear_ports_by_cmdreg = false;
	43	+ __I8255_AUTO_HAND_SHAKE = false;
42	44	set_device_name(_T("i8255 PIO"));
43	45	}
44	46	~I8255() {}
45	47
46	48	// common functions
	49	+ void initialize();
47	50	void reset();
48	51	void write_io8(uint32_t addr, uint32_t data);
49	52	uint32_t read_io8(uint32_t addr);

--- a/source/src/vm/i8259.cpp

+++ b/source/src/vm/i8259.cpp

		@@ -9,12 +9,15 @@
9	9
10	10	#include "i8259.h"
11	11
12		-#define CHIP_MASK (I8259_MAX_CHIPS - 1)
	12	+//#define CHIP_MASK (I8259_MAX_CHIPS - 1)
13	13
14	14	void I8259::initialize()
15	15	{
16	16	DEVICE::initialize();
17		- for(int c = 0; c < I8259_MAX_CHIPS; c++) {
	17	+ __I8259_MAX_CHIPS = osd->get_feature_uint32_value(_T("I8259_MAX_CHIPS"));
	18	+ if(__I8259_MAX_CHIPS >= 2) __I8259_MAX_CHIPS = 2;
	19	+ __CHIP_MASK = __I8259_MAX_CHIPS - 1;
	20	+ for(int c = 0; c < __I8259_MAX_CHIPS; c++) {
18	21	pic[c].imr = 0xff;
19	22	pic[c].irr = pic[c].isr = pic[c].prio = 0;
20	23	pic[c].icw1 = pic[c].icw2 = pic[c].icw3 = pic[c].icw4 = 0;

		@@ -25,7 +28,7 @@ void I8259::initialize()
25	28
26	29	void I8259::reset()
27	30	{
28		- for(int c = 0; c < I8259_MAX_CHIPS; c++) {
	31	+ for(int c = 0; c < __I8259_MAX_CHIPS; c++) {
29	32	pic[c].irr_tmp = 0;
30	33	pic[c].irr_tmp_id = -1;
31	34	}

		@@ -33,7 +36,7 @@ void I8259::reset()
33	36
34	37	void I8259::write_io8(uint32_t addr, uint32_t data)
35	38	{
36		- int c = (addr >> 1) & CHIP_MASK;
	39	+ int c = (addr >> 1) & __CHIP_MASK;
37	40
38	41	if(addr & 1) {
39	42	if(pic[c].icw2_r) {

		@@ -141,7 +144,7 @@ void I8259::write_io8(uint32_t addr, uint32_t data)
141	144
142	145	uint32_t I8259::read_io8(uint32_t addr)
143	146	{
144		- int c = (addr >> 1) & CHIP_MASK;
	147	+ int c = (addr >> 1) & __CHIP_MASK;
145	148
146	149	if(addr & 1) {
147	150	return pic[c].imr;

		@@ -178,7 +181,7 @@ void I8259::write_signal(int id, uint32_t data, uint32_t mask)
178	181
179	182	void I8259::event_callback(int event_id, int err)
180	183	{
181		- int c = event_id & CHIP_MASK;
	184	+ int c = event_id & __CHIP_MASK;
182	185	uint8_t irr = pic[c].irr;
183	186
184	187	pic[c].irr \|= pic[c].irr_tmp;

		@@ -199,9 +202,9 @@ void I8259::update_intr()
199	202	{
200	203	bool intr = false;
201	204
202		- for(int c = 0; c < I8259_MAX_CHIPS; c++) {
	205	+ for(int c = 0; c < __I8259_MAX_CHIPS; c++) {
203	206	uint8_t irr = pic[c].irr;
204		- if(c + 1 < I8259_MAX_CHIPS) {
	207	+ if(c + 1 < __I8259_MAX_CHIPS) {
205	208	// this is master
206	209	if(pic[c + 1].irr & (~pic[c + 1].imr)) {
207	210	// request from slave

		@@ -221,7 +224,7 @@ void I8259::update_intr()
221	224	level = (level + 1) & 7;
222	225	bit = 1 << level;
223	226	}
224		- if((c + 1 < I8259_MAX_CHIPS) && (pic[c].icw3 & bit)) {
	227	+ if((c + 1 < __I8259_MAX_CHIPS) && (pic[c].icw3 & bit)) {
225	228	// check slave
226	229	continue;
227	230	}

		@@ -281,7 +284,7 @@ void I8259::save_state(FILEIO* state_fio)
281	284	state_fio->FputUint32(STATE_VERSION);
282	285	state_fio->FputInt32(this_device_id);
283	286
284		- state_fio->Fwrite(pic, sizeof(pic), 1);
	287	+ for(int i = 0; i < __I8259_MAX_CHIPS; i++) state_fio->Fwrite(&pic[i], sizeof(struct i8259_pic_t), 1);
285	288	state_fio->FputInt32(req_chip);
286	289	state_fio->FputInt32(req_level);
287	290	state_fio->FputUint8(req_bit);

		@@ -295,7 +298,7 @@ bool I8259::load_state(FILEIO* state_fio)
295	298	if(state_fio->FgetInt32() != this_device_id) {
296	299	return false;
297	300	}
298		- state_fio->Fread(pic, sizeof(pic), 1);
	301	+ for(int i = 0; i < __I8259_MAX_CHIPS; i++) state_fio->Fread(&pic[i], sizeof(struct i8259_pic_t), 1);
299	302	req_chip = state_fio->FgetInt32();
300	303	req_level = state_fio->FgetInt32();
301	304	req_bit = state_fio->FgetUint8();

--- a/source/src/vm/i8259.h

+++ b/source/src/vm/i8259.h

		@@ -10,8 +10,8 @@
10	10	#ifndef _I8259_H_
11	11	#define _I8259_H_
12	12
13		-#include "vm.h"
14		-#include "../emu.h"
	13	+//#include "vm.h"
	14	+//#include "../emu.h"
15	15	#include "device.h"
16	16
17	17	/*

		@@ -36,19 +36,23 @@
36	36	//#define I8259_ADDR_CHIP2 4
37	37	//#define I8259_ADDR_CHIP3 6
38	38
	39	+struct i8259_pic_t {
	40	+ uint8_t imr, isr, irr, irr_tmp, prio;
	41	+ uint8_t icw1, icw2, icw3, icw4, ocw3;
	42	+ uint8_t icw2_r, icw3_r, icw4_r;
	43	+ int irr_tmp_id;
	44	+};
	45	+
39	46	class I8259 : public DEVICE
40	47	{
41	48	private:
42	49	DEVICE* d_cpu;
43		-
44		- struct {
45		- uint8_t imr, isr, irr, irr_tmp, prio;
46		- uint8_t icw1, icw2, icw3, icw4, ocw3;
47		- uint8_t icw2_r, icw3_r, icw4_r;
48		- int irr_tmp_id;
49		- } pic[I8259_MAX_CHIPS];
	50	+
	51	+ struct i8259_pic_t pic[2];
50	52	int req_chip, req_level;
51	53	uint8_t req_bit;
	54	+ uint32_t __I8259_MAX_CHIPS;
	55	+ uint32_t __CHIP_MASK;
52	56
53	57	void update_intr();
54	58

		@@ -56,6 +60,8 @@ public:
56	60	I8259(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
57	61	{
58	62	d_cpu = NULL;
	63	+ __I8259_MAX_CHIPS = 0;
	64	+ __CHIP_MASK = 0xffffffff;
59	65	set_device_name(_T("i8259 PIC"));
60	66	}
61	67	~I8259() {}

--- a/source/src/vm/j3100/dmareg.cpp

+++ b/source/src/vm/j3100/dmareg.cpp

		@@ -8,6 +8,8 @@
8	8	[ dma bank register ]
9	9	*/
10	10
	11	+#include "../vm.h"
	12	+#include "../../emu.h"
11	13	#include "dmareg.h"
12	14	#include "../i8237.h"
13	15

--- a/source/src/vm/memory.h

+++ b/source/src/vm/memory.h

		@@ -10,8 +10,8 @@
10	10	#ifndef _MEMORY_H_
11	11	#define _MEMORY_H_
12	12
13		-//#include "vm.h"
14		-//#include "../emu.h"
	13	+#include "vm.h"
	14	+#include "../emu.h"
15	15	#include "device.h"
16	16
17	17	#ifndef MEMORY_ADDR_MAX

--- a/source/src/vm/n5200/floppy.cpp

+++ b/source/src/vm/n5200/floppy.cpp

		@@ -7,6 +7,8 @@
7	7	[ floppy ]
8	8	*/
9	9
	10	+#include "../vm.h"
	11	+#include "../../emu.h"
10	12	#include "floppy.h"
11	13	#include "../i8237.h"
12	14

--- a/source/src/vm/n5200/system.cpp

+++ b/source/src/vm/n5200/system.cpp

		@@ -7,6 +7,8 @@
7	7	[ system i/o ]
8	8	*/
9	9
	10	+#include "../vm.h"
	11	+#include "../../emu.h"
10	12	#include "system.h"
11	13	#include "../i8237.h"
12	14

--- a/source/src/vm/upd7220.cpp

+++ b/source/src/vm/upd7220.cpp

		@@ -9,9 +9,12 @@
9	9	*/
10	10
11	11	#include <math.h>
	12	+#include "vm.h"
	13	+#include "../emu.h"
12	14	#include "upd7220.h"
13	15	#include "../fifo.h"
14	16
	17	+// -> See also: upd7220_base.cpp .
15	18	enum {
16	19	CMD_RESET = 0x00,
17	20	CMD_SYNC = 0x0e,

		@@ -38,7 +41,6 @@ enum {
38	41	/* unknown command (3 params) */
39	42	CMD_UNK_5A = 0x5a,
40	43	};
41		-
42	44	enum {
43	45	STAT_DRDY = 0x01,
44	46	STAT_FULL = 0x02,

		@@ -50,25 +52,9 @@ enum {
50	52	STAT_LPEN = 0x80,
51	53	};
52	54
53		-static const int vectdir[16][4] = {
54		- { 0, 1, 1, 0}, { 1, 1, 1,-1}, { 1, 0, 0,-1}, { 1,-1,-1,-1},
55		- { 0,-1,-1, 0}, {-1,-1,-1, 1}, {-1, 0, 0, 1}, {-1, 1, 1, 1},
56		- { 0, 1, 1, 1}, { 1, 1, 1, 0}, { 1, 0, 1,-1}, { 1,-1, 0,-1},
57		- { 0,-1,-1,-1}, {-1,-1,-1, 0}, {-1, 0,-1, 1}, {-1, 1, 0, 1}
58		-};
59		-
60	55	void UPD7220::initialize()
61	56	{
62		- DEVICE::initialize();
63		- for(int i = 0; i <= RT_TABLEMAX; i++) {
64		- rt[i] = (int)((double)(1 << RT_MULBIT) * (1 - sqrt(1 - pow((0.70710678118654 * i) / RT_TABLEMAX, 2))));
65		- }
66		- fo = new FIFO(0x10000);
67		-
68		- vsync = hblank = false;
69		- master = false;
70		- pitch = 40; // 640dot
71		-
	57	+ UPD7220_BASE::initialize();
72	58	// initial settings for 1st frame
73	59	vtotal = LINES_PER_FRAME;
74	60	v1 = 16;

		@@ -80,10 +66,8 @@ void UPD7220::initialize()
80	66	h1 = 80;
81	67	h2 = 29;
82	68	#endif
83		-
84	69	sync_changed = false;
85	70	vs = hc = 0;
86		-
87	71	#ifdef UPD7220_HORIZ_FREQ
88	72	horiz_freq = 0;
89	73	next_horiz_freq = UPD7220_HORIZ_FREQ;

		@@ -94,125 +78,6 @@ void UPD7220::initialize()
94	78	register_vline_event(this);
95	79	}
96	80
97		-void UPD7220::release()
98		-{
99		- fo->release();
100		- delete fo;
101		-}
102		-
103		-void UPD7220::reset()
104		-{
105		- cmd_reset();
106		-}
107		-
108		-void UPD7220::write_dma_io8(uint32_t addr, uint32_t data)
109		-{
110		- // for dma access
111		- switch(cmdreg & 0x18) {
112		- case 0x00: // low and high
113		- if(low_high) {
114		- cmd_write_sub(ead * 2 + 1, data & maskh);
115		- ead += dif;
116		- } else {
117		- cmd_write_sub(ead * 2 + 0, data & maskl);
118		- }
119		- low_high = !low_high;
120		- break;
121		- case 0x10: // low byte
122		- cmd_write_sub(ead * 2 + 0, data & maskl);
123		- ead += dif;
124		- break;
125		- case 0x18: // high byte
126		- cmd_write_sub(ead * 2 + 1, data & maskh);
127		- ead += dif;
128		- break;
129		- }
130		-}
131		-
132		-uint32_t UPD7220::read_dma_io8(uint32_t addr)
133		-{
134		- uint32_t val = 0xff;
135		-
136		- // for dma access
137		- switch(cmdreg & 0x18) {
138		- case 0x00: // low and high
139		- if(low_high) {
140		- val = read_vram(ead * 2 + 1);
141		- ead += dif;
142		- } else {
143		- val = read_vram(ead * 2 + 0);
144		- }
145		- low_high = !low_high;
146		- break;
147		- case 0x10: // low byte
148		- val = read_vram(ead * 2 + 0);
149		- ead += dif;
150		- break;
151		- case 0x18: // high byte
152		- val = read_vram(ead * 2 + 1);
153		- ead += dif;
154		- break;
155		- }
156		- return val;
157		-}
158		-
159		-void UPD7220::write_io8(uint32_t addr, uint32_t data)
160		-{
161		- switch(addr & 3) {
162		- case 0: // set parameter
163		-// this->out_debug_log(_T("\tPARAM = %2x\n"), data);
164		- if(cmdreg != -1) {
165		- if(params_count < 16) {
166		- params[params_count++] = (uint8_t)(data & 0xff);
167		- }
168		- check_cmd();
169		- if(cmdreg == -1) {
170		- params_count = 0;
171		- }
172		- }
173		- break;
174		- case 1: // process prev command if not finished
175		- if(cmdreg != -1) {
176		- process_cmd();
177		- }
178		- // set new command
179		- cmdreg = (uint8_t)(data & 0xff);
180		-// this->out_debug_log(_T("CMDREG = %2x\n"), cmdreg);
181		- params_count = 0;
182		- check_cmd();
183		- break;
184		- case 2: // set zoom
185		- zoom = data;
186		- break;
187		- case 3: // light pen request
188		- break;
189		- }
190		-}
191		-
192		-uint32_t UPD7220::read_io8(uint32_t addr)
193		-{
194		- uint32_t val;
195		-
196		- switch(addr & 3) {
197		- case 0: // status
198		- val = statreg;
199		- val \|= hblank ? STAT_HBLANK : 0;
200		- val \|= vsync ? STAT_VSYNC : 0;
201		-// val \|= (params_count == 0) ? STAT_EMPTY : 0;
202		- val \|= STAT_EMPTY;
203		- val \|= (params_count == 16) ? STAT_FULL : 0;
204		- val \|= fo->count() ? STAT_DRDY : 0;
205		- // clear busy stat
206		- statreg &= ~(STAT_DMA \| STAT_DRAW);
207		- return val;
208		- case 1: // data
209		- if(fo->count()) {
210		- return fo->read();
211		- }
212		- return 0xff;
213		- }
214		- return 0xff;
215		-}
216	81
217	82	void UPD7220::event_pre_frame()
218	83	{

		@@ -250,66 +115,6 @@ void UPD7220::event_pre_frame()
250	115	}
251	116	}
252	117
253		-void UPD7220::update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame)
254		-{
255		- cpu_clocks = new_clocks;
256		- frames_per_sec = new_frames_per_sec; // note: refer these params given from the event manager
257		- lines_per_frame = new_lines_per_frame; // because this device may be slave gdc
258		-
259		- // update event clocks
260		- vs = hc = 0;
261		-}
262		-
263		-void UPD7220::event_frame()
264		-{
265		- if(vs == 0) {
266		- vs = (int)((double)lines_per_frame * (double)v1 / (double)(v1 + v2) + 0.5);
267		- hc = (int)((double)cpu_clocks * (double)h2 / frames_per_sec / (double)lines_per_frame / (double)(h1 + h2) + 0.5);
268		- }
269		- if(++blink_cursor >= blink_rate * 4) {
270		- blink_cursor = 0;
271		- }
272		- if(++blink_attr >= blink_rate * 2) {
273		- blink_attr = 0;
274		- }
275		-}
276		-
277		-void UPD7220::event_vline(int v, int clock)
278		-{
279		- bool next = (v < vs);
280		- if(vsync != next) {
281		- write_signals(&outputs_vsync, next ? 0xffffffff : 0);
282		- vsync = next;
283		- }
284		- hblank = true;
285		- register_event_by_clock(this, 0, hc, false, NULL);
286		-}
287		-
288		-void UPD7220::event_callback(int event_id, int err)
289		-{
290		- hblank = false;
291		-}
292		-
293		-uint32_t UPD7220::cursor_addr(uint32_t mask)
294		-{
295		- if((cs[0] & 0x80) && ((cs[1] & 0x20) \|\| (blink_cursor < blink_rate * 2))) {
296		- return (ead << 1) & mask;
297		- }
298		- return -1;
299		-}
300		-
301		-int UPD7220::cursor_top()
302		-{
303		- return cs[1] & 0x1f;
304		-}
305		-
306		-int UPD7220::cursor_bottom()
307		-{
308		- return cs[2] >> 3;
309		-}
310		-
311		-// command process
312		-
313	118	void UPD7220::check_cmd()
314	119	{
315	120	// check fifo buffer and process command if enough params in fifo

		@@ -525,131 +330,6 @@ void UPD7220::process_cmd()
525	330	}
526	331	}
527	332
528		-void UPD7220::cmd_reset()
529		-{
530		- // init gdc params
531		- sync[6] = 0x90;
532		- sync[7] = 0x01;
533		- zoom = zr = zw = 0;
534		- ra[0] = ra[1] = ra[2] = 0;
535		- ra[3] = 0x1e; /0x19;/
536		- cs[0] = cs[1] = cs[2] = 0;
537		- ead = dad = 0;
538		- maskl = maskh = 0xff;
539		- mod = 0;
540		- blink_cursor = 0;
541		- blink_attr = 0;
542		- blink_rate = 16;
543		-
544		- // init fifo
545		- params_count = 0;
546		- fo->clear();
547		-
548		- // stop display and drawing
549		- start = false;
550		- statreg = 0;
551		- cmdreg = -1;
552		- cmd_write_done = false;
553		-}
554		-
555		-void UPD7220::cmd_sync()
556		-{
557		- start = ((cmdreg & 1) != 0);
558		- for(int i = 0; i < 8 && i < params_count; i++) {
559		- if(sync[i] != params[i]) {
560		- sync[i] = params[i];
561		- sync_changed = true;
562		- }
563		- }
564		- cmdreg = -1;
565		-}
566		-
567		-void UPD7220::cmd_master()
568		-{
569		- master = true;
570		- cmdreg = -1;
571		-}
572		-
573		-void UPD7220::cmd_slave()
574		-{
575		- master = false;
576		- cmdreg = -1;
577		-}
578		-
579		-void UPD7220::cmd_start()
580		-{
581		- start = true;
582		- cmdreg = -1;
583		-}
584		-
585		-void UPD7220::cmd_stop()
586		-{
587		- start = false;
588		- cmdreg = -1;
589		-}
590		-
591		-void UPD7220::cmd_zoom()
592		-{
593		- if(params_count > 0) {
594		- uint8_t tmp = params[0];
595		- zr = tmp >> 4;
596		- zw = tmp & 0x0f;
597		- cmdreg = -1;
598		- }
599		-}
600		-
601		-void UPD7220::cmd_scroll()
602		-{
603		- if(params_count > 0) {
604		- ra[cmdreg & 0x0f] = params[0];
605		- if(cmdreg < 0x7f) {
606		- cmdreg++;
607		- params_count = 0;
608		- } else {
609		- cmdreg = -1;
610		- }
611		- }
612		-}
613		-
614		-void UPD7220::cmd_csrform()
615		-{
616		- for(int i = 0; i < params_count; i++) {
617		- cs[i] = params[i];
618		- }
619		- if(params_count > 2) {
620		- cmdreg = -1;
621		- }
622		- blink_rate = (cs[1] >> 6) \| ((cs[2] & 7) << 2);
623		-}
624		-
625		-void UPD7220::cmd_pitch()
626		-{
627		- if(params_count > 0) {
628		-#ifndef UPD7220_FIXED_PITCH
629		- pitch = params[0];
630		-#endif
631		- cmdreg = -1;
632		- }
633		-}
634		-
635		-void UPD7220::cmd_lpen()
636		-{
637		- fo->write(lad & 0xff);
638		- fo->write((lad >> 8) & 0xff);
639		- fo->write((lad >> 16) & 0xff);
640		- cmdreg = -1;
641		-}
642		-
643		-void UPD7220::cmd_vectw()
644		-{
645		- for(int i = 0; i < 11 && i < params_count; i++) {
646		- vect[i] = params[i];
647		-// this->out_debug_log(_T("\tVECT[%d] = %2x\n"), i, vect[i]);
648		- }
649		- update_vect();
650		- cmdreg = -1;
651		-}
652		-
653	333	void UPD7220::cmd_vecte()
654	334	{
655	335	dx = ((ead % pitch) << 4) \| (dad & 0x0f);

		@@ -704,204 +384,118 @@ void UPD7220::cmd_texte()
704	384	cmdreg = -1;
705	385	}
706	386
707		-void UPD7220::cmd_csrw()
	387	+void UPD7220::cmd_pitch()
708	388	{
709	389	if(params_count > 0) {
710		- ead = params[0];
711		- if(params_count > 1) {
712		- ead \|= params[1] << 8;
713		- if(params_count > 2) {
714		- ead \|= params[2] << 16;
715		- cmdreg = -1;
716		- }
717		- }
718		- dad = (ead >> 20) & 0x0f;
719		- ead &= 0x3ffff;
720		- }
721		-}
722		-
723		-void UPD7220::cmd_csrr()
724		-{
725		- fo->write(ead & 0xff);
726		- fo->write((ead >> 8) & 0xff);
727		- fo->write((ead >> 16) & 0x03);
728		- fo->write(dad & 0xff);
729		- fo->write((dad >> 8) & 0xff);
730		- cmdreg = -1;
731		-}
732		-
733		-void UPD7220::cmd_mask()
734		-{
735		- if(params_count > 1) {
736		- maskl = params[0];
737		- maskh = params[1];
	390	+#ifndef UPD7220_FIXED_PITCH
	391	+ pitch = params[0];
	392	+#endif
738	393	cmdreg = -1;
739	394	}
740	395	}
741	396
742		-void UPD7220::cmd_write()
	397	+void UPD7220::draw_text()
743	398	{
744		- mod = cmdreg & 3;
745		- switch(cmdreg & 0x18) {
746		- case 0x00: // low and high
747		- if(params_count > 1) {
748		- uint8_t l = params[0] & maskl;
749		- uint8_t h = params[1] & maskh;
750		- for(int i = 0; i < dc + 1; i++) {
751		- cmd_write_sub(ead * 2 + 0, l);
752		- cmd_write_sub(ead * 2 + 1, h);
753		- ead += dif;
754		- }
755		- cmd_write_done = true;
756		- params_count = 0;
757		- }
758		- break;
759		- case 0x10: // low byte
760		- if(params_count > 0) {
761		- uint8_t l = params[0] & maskl;
762		- for(int i = 0; i < dc + 1; i++) {
763		- cmd_write_sub(ead * 2 + 0, l);
764		- ead += dif;
765		- }
766		- cmd_write_done = true;
767		- params_count = 0;
768		- }
769		- break;
770		- case 0x18: // high byte
771		- if(params_count > 0) {
772		- uint8_t h = params[0] & maskh;
773		- for(int i = 0; i < dc + 1; i++) {
774		- cmd_write_sub(ead * 2 + 1, h);
775		- ead += dif;
776		- }
777		- cmd_write_done = true;
778		- params_count = 0;
779		- }
780		- break;
781		- default: // invalid
782		- cmdreg = -1;
783		- break;
	399	+ int dir2 = dir + (sl ? 8 : 0);
	400	+ int vx1 = vectdir[dir2][0];
	401	+ int vy1 = vectdir[dir2][1];
	402	+ int vx2 = vectdir[dir2][2];
	403	+ int vy2 = vectdir[dir2][3];
	404	+ int sx = d;
	405	+ int sy = dc + 1;
	406	+#ifdef _QC10
	407	+ if(dir == 0 && sy == 40) {
	408	+ sy = 640; // ugly patch
784	409	}
785		-}
786		-
787		-void UPD7220::cmd_read()
788		-{
789		- mod = cmdreg & 3;
790		- switch(cmdreg & 0x18) {
791		- case 0x00: // low and high
792		- for(int i = 0; i < dc; i++) {
793		- fo->write(read_vram(ead * 2 + 0));
794		- fo->write(read_vram(ead * 2 + 1));
795		- ead += dif;
796		- }
797		- break;
798		- case 0x10: // low byte
799		- for(int i = 0; i < dc; i++) {
800		- fo->write(read_vram(ead * 2 + 0));
801		- ead += dif;
802		- }
803		- break;
804		- case 0x18: // high byte
805		- for(int i = 0; i < dc; i++) {
806		- fo->write(read_vram(ead * 2 + 1));
807		- ead += dif;
	410	+#endif
	411	+// this->out_debug_log(_T("\tTEXT: dx=%d,dy=%d,sx=%d,sy=%d\n"), dx, dy, sx, sy);
	412	+ int index = 15;
	413	+
	414	+ while(sy--) {
	415	+ int muly = zw + 1;
	416	+ while(muly--) {
	417	+ int cx = dx;
	418	+ int cy = dy;
	419	+ uint8_t bit = ra[index];
	420	+ int xrem = sx;
	421	+ while(xrem--) {
	422	+ pattern = (bit & 1) ? 0xffff : 0;
	423	+ bit = (bit >> 1) \| ((bit & 1) ? 0x80 : 0);
	424	+ int mulx = zw + 1;
	425	+ while(mulx--) {
	426	+ draw_pset(cx, cy);
	427	+ cx += vx1;
	428	+ cy += vy1;
	429	+ }
	430	+ }
	431	+ dx += vx2;
	432	+ dy += vy2;
808	433	}
809		- break;
810		- default: // invalid
811		- break;
812		- }
813		- reset_vect();
814		- cmdreg = -1;
815		-}
816		-
817		-void UPD7220::cmd_dmaw()
818		-{
819		- mod = cmdreg & 3;
820		- low_high = false;
821		- write_signals(&outputs_drq, 0xffffffff);
822		- reset_vect();
823		-// statreg \|= STAT_DMA;
824		- cmdreg = -1;
825		-}
826		-
827		-void UPD7220::cmd_dmar()
828		-{
829		- mod = cmdreg & 3;
830		- low_high = false;
831		- write_signals(&outputs_drq, 0xffffffff);
832		- reset_vect();
833		-// statreg \|= STAT_DMA;
834		- cmdreg = -1;
835		-}
836		-
837		-void UPD7220::cmd_unk_5a()
838		-{
839		- if(params_count > 2) {
840		- cmdreg = -1;
	434	+ index = ((index - 1) & 7) \| 8;
841	435	}
	436	+ ead = (dx >> 4) + dy * pitch;
	437	+ dad = dx & 0x0f;
842	438	}
843	439
844		-// command sub
845		-
846		-void UPD7220::cmd_write_sub(uint32_t addr, uint8_t data)
	440	+void UPD7220::draw_pset(int x, int y)
847	441	{
	442	+ uint16_t dot = pattern & 1;
	443	+ pattern = (pattern >> 1) \| (dot << 15);
	444	+ uint32_t addr = y * 80 + (x >> 3);
	445	+#ifdef UPD7220_MSB_FIRST
	446	+ uint8_t bit = 0x80 >> (x & 7);
	447	+#else
	448	+ uint8_t bit = 1 << (x & 7);
	449	+#endif
	450	+ uint8_t cur = read_vram(addr);
	451	+
848	452	switch(mod) {
849	453	case 0: // replace
850		- write_vram(addr, data);
	454	+ write_vram(addr, (cur & ~bit) \| (dot ? bit : 0));
851	455	break;
852	456	case 1: // complement
853		- write_vram(addr, read_vram(addr) ^ data);
	457	+ write_vram(addr, (cur & ~bit) \| ((cur ^ (dot ? 0xff : 0)) & bit));
854	458	break;
855	459	case 2: // reset
856		- write_vram(addr, read_vram(addr) & ~data);
	460	+ write_vram(addr, cur & (dot ? ~bit : 0xff));
857	461	break;
858	462	case 3: // set
859		- write_vram(addr, read_vram(addr) \| data);
	463	+ write_vram(addr, cur \| (dot ? bit : 0));
860	464	break;
861	465	}
862	466	}
863	467
864		-void UPD7220::write_vram(uint32_t addr, uint8_t data)
865		-{
866		- if(vram != NULL && addr < vram_size) {
867		- vram[addr] = data;
868		- }
869		-}
870		-
871		-uint8_t UPD7220::read_vram(uint32_t addr)
	468	+void UPD7220::write_io8(uint32_t addr, uint32_t data)
872	469	{
873		- if(vram != NULL && addr < vram_size) {
874		- uint8_t mask = (addr & 1) ? (vram_data_mask >> 8) : (vram_data_mask & 0xff);
875		- return (vram[addr] & mask) \| ~mask;
	470	+ switch(addr & 3) {
	471	+ case 0: // set parameter
	472	+// this->out_debug_log(_T("\tPARAM = %2x\n"), data);
	473	+ if(cmdreg != -1) {
	474	+ if(params_count < 16) {
	475	+ params[params_count++] = (uint8_t)(data & 0xff);
	476	+ }
	477	+ check_cmd();
	478	+ if(cmdreg == -1) {
	479	+ params_count = 0;
	480	+ }
	481	+ }
	482	+ break;
	483	+ case 1: // process prev command if not finished
	484	+ if(cmdreg != -1) {
	485	+ process_cmd();
	486	+ }
	487	+ // set new command
	488	+ cmdreg = (uint8_t)(data & 0xff);
	489	+// this->out_debug_log(_T("CMDREG = %2x\n"), cmdreg);
	490	+ params_count = 0;
	491	+ check_cmd();
	492	+ break;
	493	+ case 2: // set zoom
	494	+ zoom = data;
	495	+ break;
	496	+ case 3: // light pen request
	497	+ break;
876	498	}
877		- return 0xff;
878		-}
879		-
880		-void UPD7220::update_vect()
881		-{
882		- dir = vect[0] & 7;
883		- dif = vectdir[dir][0] + vectdir[dir][1] * pitch;
884		- sl = vect[0] & 0x80;
885		- dc = (vect[1] \| (vect[ 2] << 8)) & 0x3fff;
886		- d = (vect[3] \| (vect[ 4] << 8)) & 0x3fff;
887		- d2 = (vect[5] \| (vect[ 6] << 8)) & 0x3fff;
888		- d1 = (vect[7] \| (vect[ 8] << 8)) & 0x3fff;
889		- dm = (vect[9] \| (vect[10] << 8)) & 0x3fff;
890		-}
891		-
892		-void UPD7220::reset_vect()
893		-{
894		- vect[ 1] = 0x00;
895		- vect[ 2] = 0x00;
896		- vect[ 3] = 0x08;
897		- vect[ 4] = 0x00;
898		- vect[ 5] = 0x08;
899		- vect[ 6] = 0x00;
900		- vect[ 7] = 0x00;
901		- vect[ 8] = 0x00;
902		- vect[ 9] = 0x00;
903		- vect[10] = 0x00;
904		- update_vect();
905	499	}
906	500
907	501	// draw

		@@ -1121,77 +715,6 @@ void UPD7220::draw_vectr()
1121	715	dad = dx & 0x0f;
1122	716	}
1123	717
1124		-void UPD7220::draw_text()
1125		-{
1126		- int dir2 = dir + (sl ? 8 : 0);
1127		- int vx1 = vectdir[dir2][0];
1128		- int vy1 = vectdir[dir2][1];
1129		- int vx2 = vectdir[dir2][2];
1130		- int vy2 = vectdir[dir2][3];
1131		- int sx = d;
1132		- int sy = dc + 1;
1133		-#ifdef _QC10
1134		- if(dir == 0 && sy == 40) {
1135		- sy = 640; // ugly patch
1136		- }
1137		-#endif
1138		-// this->out_debug_log(_T("\tTEXT: dx=%d,dy=%d,sx=%d,sy=%d\n"), dx, dy, sx, sy);
1139		- int index = 15;
1140		-
1141		- while(sy--) {
1142		- int muly = zw + 1;
1143		- while(muly--) {
1144		- int cx = dx;
1145		- int cy = dy;
1146		- uint8_t bit = ra[index];
1147		- int xrem = sx;
1148		- while(xrem--) {
1149		- pattern = (bit & 1) ? 0xffff : 0;
1150		- bit = (bit >> 1) \| ((bit & 1) ? 0x80 : 0);
1151		- int mulx = zw + 1;
1152		- while(mulx--) {
1153		- draw_pset(cx, cy);
1154		- cx += vx1;
1155		- cy += vy1;
1156		- }
1157		- }
1158		- dx += vx2;
1159		- dy += vy2;
1160		- }
1161		- index = ((index - 1) & 7) \| 8;
1162		- }
1163		- ead = (dx >> 4) + dy * pitch;
1164		- dad = dx & 0x0f;
1165		-}
1166		-
1167		-void UPD7220::draw_pset(int x, int y)
1168		-{
1169		- uint16_t dot = pattern & 1;
1170		- pattern = (pattern >> 1) \| (dot << 15);
1171		- uint32_t addr = y * 80 + (x >> 3);
1172		-#ifdef UPD7220_MSB_FIRST
1173		- uint8_t bit = 0x80 >> (x & 7);
1174		-#else
1175		- uint8_t bit = 1 << (x & 7);
1176		-#endif
1177		- uint8_t cur = read_vram(addr);
1178		-
1179		- switch(mod) {
1180		- case 0: // replace
1181		- write_vram(addr, (cur & ~bit) \| (dot ? bit : 0));
1182		- break;
1183		- case 1: // complement
1184		- write_vram(addr, (cur & ~bit) \| ((cur ^ (dot ? 0xff : 0)) & bit));
1185		- break;
1186		- case 2: // reset
1187		- write_vram(addr, cur & (dot ? ~bit : 0xff));
1188		- break;
1189		- case 3: // set
1190		- write_vram(addr, cur \| (dot ? bit : 0));
1191		- break;
1192		- }
1193		-}
1194		-
1195	718	#define STATE_VERSION 1
1196	719
1197	720	void UPD7220::save_state(FILEIO* state_fio)

--- a/source/src/vm/upd7220.h

+++ b/source/src/vm/upd7220.h

		@@ -11,8 +11,8 @@
11	11	#ifndef _UPD7220_H_
12	12	#define _UPD7220_H_
13	13
14		-#include "vm.h"
15		-#include "../emu.h"
	14	+//#include "vm.h"
	15	+//#include "../emu.h"
16	16	#include "device.h"
17	17
18	18	#define MODE_MIX ((sync[0] & 0x22) == 0x00)

		@@ -25,9 +25,9 @@
25	25
26	26	class FIFO;
27	27
28		-class UPD7220 : public DEVICE
	28	+class UPD7220_BASE : public DEVICE
29	29	{
30		-private:
	30	+protected:
31	31	// output signals
32	32	outputs_t outputs_drq;
33	33	outputs_t outputs_vsync;

		@@ -64,9 +64,6 @@ private:
64	64	bool cmd_write_done;
65	65
66	66	int cpu_clocks;
67		-#ifdef UPD7220_HORIZ_FREQ
68		- int horiz_freq, next_horiz_freq;
69		-#endif
70	67	double frames_per_sec;
71	68	int lines_per_frame;
72	69

		@@ -80,10 +77,16 @@ private:
80	77	int dx, dy; // from ead, dad
81	78	int dir, dif, sl, dc, d, d2, d1, dm;
82	79	uint16_t pattern;
	80	+ const int vectdir[16][4] = {
	81	+ { 0, 1, 1, 0}, { 1, 1, 1,-1}, { 1, 0, 0,-1}, { 1,-1,-1,-1},
	82	+ { 0,-1,-1, 0}, {-1,-1,-1, 1}, {-1, 0, 0, 1}, {-1, 1, 1, 1},
	83	+ { 0, 1, 1, 1}, { 1, 1, 1, 0}, { 1, 0, 1,-1}, { 1,-1, 0,-1},
	84	+ { 0,-1,-1,-1}, {-1,-1,-1, 0}, {-1, 0,-1, 1}, {-1, 1, 0, 1}
	85	+ };
83	86
84	87	// command
85		- void check_cmd();
86		- void process_cmd();
	88	+ //void check_cmd();
	89	+ //void process_cmd();
87	90
88	91	void cmd_reset();
89	92	void cmd_sync();

		@@ -94,11 +97,11 @@ private:
94	97	void cmd_zoom();
95	98	void cmd_scroll();
96	99	void cmd_csrform();
97		- void cmd_pitch();
	100	+ //void cmd_pitch();
98	101	void cmd_lpen();
99	102	void cmd_vectw();
100		- void cmd_vecte();
101		- void cmd_texte();
	103	+ //void cmd_vecte();
	104	+ //void cmd_texte();
102	105	void cmd_csrw();
103	106	void cmd_csrr();
104	107	void cmd_mask();

		@@ -114,15 +117,10 @@ private:
114	117	void update_vect();
115	118	void reset_vect();
116	119
117		- void draw_vectl();
118		- void draw_vectt();
119		- void draw_vectc();
120		- void draw_vectr();
121		- void draw_text();
122		- void draw_pset(int x, int y);
123		-
	120	+ //virtual void draw_text();
	121	+ //virtual void draw_pset(int x, int y);
124	122	public:
125		- UPD7220(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
	123	+ UPD7220_BASE(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
126	124	{
127	125	initialize_output_signals(&outputs_drq);
128	126	initialize_output_signals(&outputs_vsync);

		@@ -131,23 +129,23 @@ public:
131	129	vram_data_mask = 0xffff;
132	130	set_device_name(_T("uPD7220 GDC"));
133	131	}
134		- ~UPD7220() {}
	132	+ ~UPD7220_BASE() {}
135	133
136	134	// common functions
137		- void initialize();
	135	+ virtual void initialize();
138	136	void release();
139	137	void reset();
140	138	void write_dma_io8(uint32_t addr, uint32_t data);
141	139	uint32_t read_dma_io8(uint32_t addr);
142		- void write_io8(uint32_t addr, uint32_t data);
	140	+ virtual void write_io8(uint32_t addr, uint32_t data);
143	141	uint32_t read_io8(uint32_t addr);
144		- void event_pre_frame();
	142	+ virtual void event_pre_frame();
145	143	void event_frame();
146	144	void event_vline(int v, int clock);
147	145	void event_callback(int event_id, int err);
148	146	void update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame);
149		- void save_state(FILEIO* state_fio);
150		- bool load_state(FILEIO* state_fio);
	147	+ virtual void save_state(FILEIO* state_fio) {}
	148	+ virtual bool load_state(FILEIO* state_fio) { return false; }
151	149
152	150	// unique functions
153	151	void set_context_drq(DEVICE* device, int id, uint32_t mask)

		@@ -169,12 +167,6 @@ public:
169	167	vram_size = size;
170	168	vram_data_mask = mask;
171	169	}
172		-#ifdef UPD7220_HORIZ_FREQ
173		- void set_horiz_freq(int freq)
174		- {
175		- next_horiz_freq = freq;
176		- }
177		-#endif
178	170	uint8_t* get_sync()
179	171	{
180	172	return sync;

		@@ -208,5 +200,47 @@ public:
208	200	}
209	201	};
210	202
	203	+
	204	+class UPD7220 : public UPD7220_BASE
	205	+{
	206	+private:
	207	+#ifdef UPD7220_HORIZ_FREQ
	208	+ int horiz_freq, next_horiz_freq;
	209	+#endif
	210	+private:
	211	+ void check_cmd();
	212	+ void process_cmd();
	213	+
	214	+ void draw_vectl();
	215	+ void draw_vectt();
	216	+ void draw_vectc();
	217	+ void draw_vectr();
	218	+
	219	+ void cmd_vecte();
	220	+ void cmd_texte();
	221	+ void cmd_pitch();
	222	+
	223	+ void draw_text();
	224	+ void draw_pset(int x, int y);
	225	+public:
	226	+ UPD7220(VM* parent_vm, EMU* parent_emu) : UPD7220_BASE(parent_vm, parent_emu)
	227	+ {
	228	+ }
	229	+ ~UPD7220() {}
	230	+ void initialize();
	231	+ void event_pre_frame();
	232	+ virtual void write_io8(uint32_t addr, uint32_t data);
	233	+
	234	+ void save_state(FILEIO* state_fio);
	235	+ bool load_state(FILEIO* state_fio);
	236	+
	237	+#ifdef UPD7220_HORIZ_FREQ
	238	+ void set_horiz_freq(int freq)
	239	+ {
	240	+ next_horiz_freq = freq;
	241	+ }
	242	+#endif
	243	+};
	244	+
211	245	#endif
212	246

--- /dev/null

+++ b/source/src/vm/upd7220_base.cpp

		@@ -0,0 +1,518 @@
	1	+/*
	2	+ Skelton for retropc emulator
	3	+
	4	+ Origin : Neko Project 2
	5	+ Author : Takeda.Toshiya
	6	+ Date : 2006.12.06 -
	7	+
	8	+ [ uPD7220 ]
	9	+*/
	10	+
	11	+#include <math.h>
	12	+#include "upd7220.h"
	13	+#include "../fifo.h"
	14	+// -> See also: upd7220_base.cpp .
	15	+
	16	+
	17	+enum {
	18	+ STAT_DRDY = 0x01,
	19	+ STAT_FULL = 0x02,
	20	+ STAT_EMPTY = 0x04,
	21	+ STAT_DRAW = 0x08,
	22	+ STAT_DMA = 0x10,
	23	+ STAT_VSYNC = 0x20,
	24	+ STAT_HBLANK = 0x40,
	25	+ STAT_LPEN = 0x80,
	26	+};
	27	+
	28	+
	29	+void UPD7220_BASE::initialize()
	30	+{
	31	+ DEVICE::initialize();
	32	+ for(int i = 0; i <= RT_TABLEMAX; i++) {
	33	+ rt[i] = (int)((double)(1 << RT_MULBIT) * (1 - sqrt(1 - pow((0.70710678118654 * i) / RT_TABLEMAX, 2))));
	34	+ }
	35	+ fo = new FIFO(0x10000);
	36	+
	37	+ vsync = hblank = false;
	38	+ master = false;
	39	+ pitch = 40; // 640dot
	40	+
	41	+ // -> upd7220.cpp
	42	+}
	43	+
	44	+void UPD7220_BASE::release()
	45	+{
	46	+ fo->release();
	47	+ delete fo;
	48	+}
	49	+
	50	+void UPD7220_BASE::reset()
	51	+{
	52	+ cmd_reset();
	53	+}
	54	+
	55	+void UPD7220_BASE::write_dma_io8(uint32_t addr, uint32_t data)
	56	+{
	57	+ // for dma access
	58	+ switch(cmdreg & 0x18) {
	59	+ case 0x00: // low and high
	60	+ if(low_high) {
	61	+ cmd_write_sub(ead * 2 + 1, data & maskh);
	62	+ ead += dif;
	63	+ } else {
	64	+ cmd_write_sub(ead * 2 + 0, data & maskl);
	65	+ }
	66	+ low_high = !low_high;
	67	+ break;
	68	+ case 0x10: // low byte
	69	+ cmd_write_sub(ead * 2 + 0, data & maskl);
	70	+ ead += dif;
	71	+ break;
	72	+ case 0x18: // high byte
	73	+ cmd_write_sub(ead * 2 + 1, data & maskh);
	74	+ ead += dif;
	75	+ break;
	76	+ }
	77	+}
	78	+
	79	+uint32_t UPD7220_BASE::read_dma_io8(uint32_t addr)
	80	+{
	81	+ uint32_t val = 0xff;
	82	+
	83	+ // for dma access
	84	+ switch(cmdreg & 0x18) {
	85	+ case 0x00: // low and high
	86	+ if(low_high) {
	87	+ val = read_vram(ead * 2 + 1);
	88	+ ead += dif;
	89	+ } else {
	90	+ val = read_vram(ead * 2 + 0);
	91	+ }
	92	+ low_high = !low_high;
	93	+ break;
	94	+ case 0x10: // low byte
	95	+ val = read_vram(ead * 2 + 0);
	96	+ ead += dif;
	97	+ break;
	98	+ case 0x18: // high byte
	99	+ val = read_vram(ead * 2 + 1);
	100	+ ead += dif;
	101	+ break;
	102	+ }
	103	+ return val;
	104	+}
	105	+
	106	+void UPD7220_BASE::write_io8(uint32_t addr, uint32_t data)
	107	+{
	108	+ // Dummy function
	109	+}
	110	+
	111	+uint32_t UPD7220_BASE::read_io8(uint32_t addr)
	112	+{
	113	+ uint32_t val;
	114	+
	115	+ switch(addr & 3) {
	116	+ case 0: // status
	117	+ val = statreg;
	118	+ val \|= hblank ? STAT_HBLANK : 0;
	119	+ val \|= vsync ? STAT_VSYNC : 0;
	120	+// val \|= (params_count == 0) ? STAT_EMPTY : 0;
	121	+ val \|= STAT_EMPTY;
	122	+ val \|= (params_count == 16) ? STAT_FULL : 0;
	123	+ val \|= fo->count() ? STAT_DRDY : 0;
	124	+ // clear busy stat
	125	+ statreg &= ~(STAT_DMA \| STAT_DRAW);
	126	+ return val;
	127	+ case 1: // data
	128	+ if(fo->count()) {
	129	+ return fo->read();
	130	+ }
	131	+ return 0xff;
	132	+ }
	133	+ return 0xff;
	134	+}
	135	+
	136	+void UPD7220_BASE::event_pre_frame()
	137	+{
	138	+ // Dummy func.
	139	+}
	140	+
	141	+void UPD7220_BASE::update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame)
	142	+{
	143	+ cpu_clocks = new_clocks;
	144	+ frames_per_sec = new_frames_per_sec; // note: refer these params given from the event manager
	145	+ lines_per_frame = new_lines_per_frame; // because this device may be slave gdc
	146	+
	147	+ // update event clocks
	148	+ vs = hc = 0;
	149	+}
	150	+
	151	+void UPD7220_BASE::event_frame()
	152	+{
	153	+ if(vs == 0) {
	154	+ vs = (int)((double)lines_per_frame * (double)v1 / (double)(v1 + v2) + 0.5);
	155	+ hc = (int)((double)cpu_clocks * (double)h2 / frames_per_sec / (double)lines_per_frame / (double)(h1 + h2) + 0.5);
	156	+ }
	157	+ if(++blink_cursor >= blink_rate * 4) {
	158	+ blink_cursor = 0;
	159	+ }
	160	+ if(++blink_attr >= blink_rate * 2) {
	161	+ blink_attr = 0;
	162	+ }
	163	+}
	164	+
	165	+void UPD7220_BASE::event_vline(int v, int clock)
	166	+{
	167	+ bool next = (v < vs);
	168	+ if(vsync != next) {
	169	+ write_signals(&outputs_vsync, next ? 0xffffffff : 0);
	170	+ vsync = next;
	171	+ }
	172	+ hblank = true;
	173	+ register_event_by_clock(this, 0, hc, false, NULL);
	174	+}
	175	+
	176	+void UPD7220_BASE::event_callback(int event_id, int err)
	177	+{
	178	+ hblank = false;
	179	+}
	180	+
	181	+uint32_t UPD7220_BASE::cursor_addr(uint32_t mask)
	182	+{
	183	+ if((cs[0] & 0x80) && ((cs[1] & 0x20) \|\| (blink_cursor < blink_rate * 2))) {
	184	+ return (ead << 1) & mask;
	185	+ }
	186	+ return -1;
	187	+}
	188	+
	189	+int UPD7220_BASE::cursor_top()
	190	+{
	191	+ return cs[1] & 0x1f;
	192	+}
	193	+
	194	+int UPD7220_BASE::cursor_bottom()
	195	+{
	196	+ return cs[2] >> 3;
	197	+}
	198	+
	199	+// command process
	200	+
	201	+void UPD7220_BASE::cmd_reset()
	202	+{
	203	+ // init gdc params
	204	+ sync[6] = 0x90;
	205	+ sync[7] = 0x01;
	206	+ zoom = zr = zw = 0;
	207	+ ra[0] = ra[1] = ra[2] = 0;
	208	+ ra[3] = 0x1e; /0x19;/
	209	+ cs[0] = cs[1] = cs[2] = 0;
	210	+ ead = dad = 0;
	211	+ maskl = maskh = 0xff;
	212	+ mod = 0;
	213	+ blink_cursor = 0;
	214	+ blink_attr = 0;
	215	+ blink_rate = 16;
	216	+
	217	+ // init fifo
	218	+ params_count = 0;
	219	+ fo->clear();
	220	+
	221	+ // stop display and drawing
	222	+ start = false;
	223	+ statreg = 0;
	224	+ cmdreg = -1;
	225	+ cmd_write_done = false;
	226	+}
	227	+
	228	+void UPD7220_BASE::cmd_sync()
	229	+{
	230	+ start = ((cmdreg & 1) != 0);
	231	+ for(int i = 0; i < 8 && i < params_count; i++) {
	232	+ if(sync[i] != params[i]) {
	233	+ sync[i] = params[i];
	234	+ sync_changed = true;
	235	+ }
	236	+ }
	237	+ cmdreg = -1;
	238	+}
	239	+
	240	+void UPD7220_BASE::cmd_master()
	241	+{
	242	+ master = true;
	243	+ cmdreg = -1;
	244	+}
	245	+
	246	+void UPD7220_BASE::cmd_slave()
	247	+{
	248	+ master = false;
	249	+ cmdreg = -1;
	250	+}
	251	+
	252	+void UPD7220_BASE::cmd_start()
	253	+{
	254	+ start = true;
	255	+ cmdreg = -1;
	256	+}
	257	+
	258	+void UPD7220_BASE::cmd_stop()
	259	+{
	260	+ start = false;
	261	+ cmdreg = -1;
	262	+}
	263	+
	264	+void UPD7220_BASE::cmd_zoom()
	265	+{
	266	+ if(params_count > 0) {
	267	+ uint8_t tmp = params[0];
	268	+ zr = tmp >> 4;
	269	+ zw = tmp & 0x0f;
	270	+ cmdreg = -1;
	271	+ }
	272	+}
	273	+
	274	+void UPD7220_BASE::cmd_scroll()
	275	+{
	276	+ if(params_count > 0) {
	277	+ ra[cmdreg & 0x0f] = params[0];
	278	+ if(cmdreg < 0x7f) {
	279	+ cmdreg++;
	280	+ params_count = 0;
	281	+ } else {
	282	+ cmdreg = -1;
	283	+ }
	284	+ }
	285	+}
	286	+
	287	+void UPD7220_BASE::cmd_csrform()
	288	+{
	289	+ for(int i = 0; i < params_count; i++) {
	290	+ cs[i] = params[i];
	291	+ }
	292	+ if(params_count > 2) {
	293	+ cmdreg = -1;
	294	+ }
	295	+ blink_rate = (cs[1] >> 6) \| ((cs[2] & 7) << 2);
	296	+}
	297	+
	298	+void UPD7220_BASE::cmd_lpen()
	299	+{
	300	+ fo->write(lad & 0xff);
	301	+ fo->write((lad >> 8) & 0xff);
	302	+ fo->write((lad >> 16) & 0xff);
	303	+ cmdreg = -1;
	304	+}
	305	+
	306	+void UPD7220_BASE::cmd_vectw()
	307	+{
	308	+ for(int i = 0; i < 11 && i < params_count; i++) {
	309	+ vect[i] = params[i];
	310	+// this->out_debug_log(_T("\tVECT[%d] = %2x\n"), i, vect[i]);
	311	+ }
	312	+ update_vect();
	313	+ cmdreg = -1;
	314	+}
	315	+
	316	+
	317	+void UPD7220_BASE::cmd_csrw()
	318	+{
	319	+ if(params_count > 0) {
	320	+ ead = params[0];
	321	+ if(params_count > 1) {
	322	+ ead \|= params[1] << 8;
	323	+ if(params_count > 2) {
	324	+ ead \|= params[2] << 16;
	325	+ cmdreg = -1;
	326	+ }
	327	+ }
	328	+ dad = (ead >> 20) & 0x0f;
	329	+ ead &= 0x3ffff;
	330	+ }
	331	+}
	332	+
	333	+void UPD7220_BASE::cmd_csrr()
	334	+{
	335	+ fo->write(ead & 0xff);
	336	+ fo->write((ead >> 8) & 0xff);
	337	+ fo->write((ead >> 16) & 0x03);
	338	+ fo->write(dad & 0xff);
	339	+ fo->write((dad >> 8) & 0xff);
	340	+ cmdreg = -1;
	341	+}
	342	+
	343	+void UPD7220_BASE::cmd_mask()
	344	+{
	345	+ if(params_count > 1) {
	346	+ maskl = params[0];
	347	+ maskh = params[1];
	348	+ cmdreg = -1;
	349	+ }
	350	+}
	351	+
	352	+void UPD7220_BASE::cmd_write()
	353	+{
	354	+ mod = cmdreg & 3;
	355	+ switch(cmdreg & 0x18) {
	356	+ case 0x00: // low and high
	357	+ if(params_count > 1) {
	358	+ uint8_t l = params[0] & maskl;
	359	+ uint8_t h = params[1] & maskh;
	360	+ for(int i = 0; i < dc + 1; i++) {
	361	+ cmd_write_sub(ead * 2 + 0, l);
	362	+ cmd_write_sub(ead * 2 + 1, h);
	363	+ ead += dif;
	364	+ }
	365	+ cmd_write_done = true;
	366	+ params_count = 0;
	367	+ }
	368	+ break;
	369	+ case 0x10: // low byte
	370	+ if(params_count > 0) {
	371	+ uint8_t l = params[0] & maskl;
	372	+ for(int i = 0; i < dc + 1; i++) {
	373	+ cmd_write_sub(ead * 2 + 0, l);
	374	+ ead += dif;
	375	+ }
	376	+ cmd_write_done = true;
	377	+ params_count = 0;
	378	+ }
	379	+ break;
	380	+ case 0x18: // high byte
	381	+ if(params_count > 0) {
	382	+ uint8_t h = params[0] & maskh;
	383	+ for(int i = 0; i < dc + 1; i++) {
	384	+ cmd_write_sub(ead * 2 + 1, h);
	385	+ ead += dif;
	386	+ }
	387	+ cmd_write_done = true;
	388	+ params_count = 0;
	389	+ }
	390	+ break;
	391	+ default: // invalid
	392	+ cmdreg = -1;
	393	+ break;
	394	+ }
	395	+}
	396	+
	397	+void UPD7220_BASE::cmd_read()
	398	+{
	399	+ mod = cmdreg & 3;
	400	+ switch(cmdreg & 0x18) {
	401	+ case 0x00: // low and high
	402	+ for(int i = 0; i < dc; i++) {
	403	+ fo->write(read_vram(ead * 2 + 0));
	404	+ fo->write(read_vram(ead * 2 + 1));
	405	+ ead += dif;
	406	+ }
	407	+ break;
	408	+ case 0x10: // low byte
	409	+ for(int i = 0; i < dc; i++) {
	410	+ fo->write(read_vram(ead * 2 + 0));
	411	+ ead += dif;
	412	+ }
	413	+ break;
	414	+ case 0x18: // high byte
	415	+ for(int i = 0; i < dc; i++) {
	416	+ fo->write(read_vram(ead * 2 + 1));
	417	+ ead += dif;
	418	+ }
	419	+ break;
	420	+ default: // invalid
	421	+ break;
	422	+ }
	423	+ reset_vect();
	424	+ cmdreg = -1;
	425	+}
	426	+
	427	+void UPD7220_BASE::cmd_dmaw()
	428	+{
	429	+ mod = cmdreg & 3;
	430	+ low_high = false;
	431	+ write_signals(&outputs_drq, 0xffffffff);
	432	+ reset_vect();
	433	+// statreg \|= STAT_DMA;
	434	+ cmdreg = -1;
	435	+}
	436	+
	437	+void UPD7220_BASE::cmd_dmar()
	438	+{
	439	+ mod = cmdreg & 3;
	440	+ low_high = false;
	441	+ write_signals(&outputs_drq, 0xffffffff);
	442	+ reset_vect();
	443	+// statreg \|= STAT_DMA;
	444	+ cmdreg = -1;
	445	+}
	446	+
	447	+void UPD7220_BASE::cmd_unk_5a()
	448	+{
	449	+ if(params_count > 2) {
	450	+ cmdreg = -1;
	451	+ }
	452	+}
	453	+
	454	+// command sub
	455	+
	456	+void UPD7220_BASE::cmd_write_sub(uint32_t addr, uint8_t data)
	457	+{
	458	+ switch(mod) {
	459	+ case 0: // replace
	460	+ write_vram(addr, data);
	461	+ break;
	462	+ case 1: // complement
	463	+ write_vram(addr, read_vram(addr) ^ data);
	464	+ break;
	465	+ case 2: // reset
	466	+ write_vram(addr, read_vram(addr) & ~data);
	467	+ break;
	468	+ case 3: // set
	469	+ write_vram(addr, read_vram(addr) \| data);
	470	+ break;
	471	+ }
	472	+}
	473	+
	474	+void UPD7220_BASE::write_vram(uint32_t addr, uint8_t data)
	475	+{
	476	+ if(vram != NULL && addr < vram_size) {
	477	+ vram[addr] = data;
	478	+ }
	479	+}
	480	+
	481	+uint8_t UPD7220_BASE::read_vram(uint32_t addr)
	482	+{
	483	+ if(vram != NULL && addr < vram_size) {
	484	+ uint8_t mask = (addr & 1) ? (vram_data_mask >> 8) : (vram_data_mask & 0xff);
	485	+ return (vram[addr] & mask) \| ~mask;
	486	+ }
	487	+ return 0xff;
	488	+}
	489	+
	490	+void UPD7220_BASE::update_vect()
	491	+{
	492	+ dir = vect[0] & 7;
	493	+ dif = vectdir[dir][0] + vectdir[dir][1] * pitch;
	494	+ sl = vect[0] & 0x80;
	495	+ dc = (vect[1] \| (vect[ 2] << 8)) & 0x3fff;
	496	+ d = (vect[3] \| (vect[ 4] << 8)) & 0x3fff;
	497	+ d2 = (vect[5] \| (vect[ 6] << 8)) & 0x3fff;
	498	+ d1 = (vect[7] \| (vect[ 8] << 8)) & 0x3fff;
	499	+ dm = (vect[9] \| (vect[10] << 8)) & 0x3fff;
	500	+}
	501	+
	502	+void UPD7220_BASE::reset_vect()
	503	+{
	504	+ vect[ 1] = 0x00;
	505	+ vect[ 2] = 0x00;
	506	+ vect[ 3] = 0x08;
	507	+ vect[ 4] = 0x00;
	508	+ vect[ 5] = 0x08;
	509	+ vect[ 6] = 0x00;
	510	+ vect[ 7] = 0x00;
	511	+ vect[ 8] = 0x00;
	512	+ vect[ 9] = 0x00;
	513	+ vect[10] = 0x00;
	514	+ update_vect();
	515	+}
	516	+
	517	+
	518	+

--- a/source/src/vm/z80sio.cpp

+++ b/source/src/vm/z80sio.cpp

		@@ -85,16 +85,23 @@
85	85	void Z80SIO::initialize()
86	86	{
87	87	DEVICE::initialize();
	88	+ __HAS_UPD7201 = osd->check_feature(_T("HAS_UPD7201"));
	89	+ __SIO_DEBUG = osd->check_feature(_T("SIO_DEBUG"));
	90	+
88	91	for(int ch = 0; ch < 2; ch++) {
89		-#ifdef HAS_UPD7201
90		- port[ch].send = new FIFO(16);
91		- port[ch].recv = new FIFO(16);
92		- port[ch].rtmp = new FIFO(16);
93		-#else
94		- port[ch].send = new FIFO(1);
95		- port[ch].recv = new FIFO(4);
96		- port[ch].rtmp = new FIFO(8);
97		-#endif
	92	+//#ifdef HAS_UPD7201
	93	+ if(__HAS_UPD7201) {
	94	+ port[ch].send = new FIFO(16);
	95	+ port[ch].recv = new FIFO(16);
	96	+ port[ch].rtmp = new FIFO(16);
	97	+ } else {
	98	+//#else
	99	+ port[ch].send = new FIFO(1);
	100	+ port[ch].recv = new FIFO(4);
	101	+ port[ch].rtmp = new FIFO(8);
	102	+ port[ch].tx_count_hi = 0;
	103	+ }
	104	+//#endif
98	105	// input signals
99	106	port[ch].dcd = true;
100	107	port[ch].cts = true;

		@@ -112,9 +119,9 @@ void Z80SIO::reset()
112	119	port[ch].over_flow = false;
113	120	port[ch].under_run = false;
114	121	port[ch].abort = false;
115		-#ifdef HAS_UPD7201
	122	+//#ifdef HAS_UPD7201
116	123	port[ch].tx_count = 0;
117		-#endif
	124	+//#endif
118	125	port[ch].send->clear();
119	126	port[ch].recv->clear();
120	127	port[ch].rtmp->clear();

		@@ -201,20 +208,20 @@ void Z80SIO::write_io8(uint32_t addr, uint32_t data)
201	208	} else {
202	209	CANCEL_SEND_EVENT(ch);
203	210	}
204		-#ifndef HAS_UPD7201
205		- port[ch].send->clear();
206		-#endif
	211	+//#ifndef HAS_UPD7201
	212	+ if(!__HAS_UPD7201) port[ch].send->clear();
	213	+//#endif
207	214	port[ch].send->write(data);
208		-#ifdef HAS_UPD7201
209		- port[ch].tx_count++;
210		-#endif
	215	+//#ifdef HAS_UPD7201
	216	+ if(__HAS_UPD7201) port[ch].tx_count++;
	217	+//#endif
211	218	break;
212	219	case 1:
213	220	case 3:
214	221	// control
215		-#ifdef SIO_DEBUG
216		-// this->out_debug_log(_T("Z80SIO: ch=%d WR[%d]=%2x\n"), ch, port[ch].pointer, data);
217		-#endif
	222	+//#ifdef SIO_DEBUG
	223	+// if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d WR[%d]=%2x\n"), ch, port[ch].pointer, data);
	224	+//#endif
218	225	switch(port[ch].pointer) {
219	226	case 0:
220	227	switch(data & 0x38) {

		@@ -231,9 +238,9 @@ void Z80SIO::write_io8(uint32_t addr, uint32_t data)
231	238	port[ch].nextrecv_intr = false;
232	239	port[ch].first_data = false;
233	240	port[ch].over_flow = false;
234		-#ifdef HAS_UPD7201
235		- port[ch].tx_count = 0; // is this correct ???
236		-#endif
	241	+//#ifdef HAS_UPD7201
	242	+ if(__HAS_UPD7201) port[ch].tx_count = 0; // is this correct ???
	243	+//#endif
237	244	port[ch].send->clear();
238	245	port[ch].recv->clear();
239	246	port[ch].rtmp->clear();

		@@ -316,14 +323,14 @@ void Z80SIO::write_io8(uint32_t addr, uint32_t data)
316	323	if((data & 0x11) == 0x11) {
317	324	// enter hunt/sync phase
318	325	if(MONOSYNC(ch)) {
319		-#ifdef SIO_DEBUG
320		- this->out_debug_log(_T("Z80SIO: ch=%d enter hunt/sync phase (monosync)\n"), ch);
321		-#endif
	326	+//#ifdef SIO_DEBUG
	327	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d enter hunt/sync phase (monosync)\n"), ch);
	328	+//#endif
322	329	port[ch].sync_bit = BIT_SYNC1;
323	330	} else if(BISYNC(ch)) {
324		-#ifdef SIO_DEBUG
325		- this->out_debug_log(_T("Z80SIO: ch=%d enter hunt/sync phase (bisync)\n"), ch);
326		-#endif
	331	+//#ifdef SIO_DEBUG
	332	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d enter hunt/sync phase (bisync)\n"), ch);
	333	+//#endif
327	334	port[ch].sync_bit = BIT_SYNC1 \| BIT_SYNC2;
328	335	}
329	336	port[ch].sync = false;

		@@ -434,14 +441,18 @@ uint32_t Z80SIO::read_io8(uint32_t addr)
434	441	}
435	442	} else if(port[ch].pointer == 2) {
436	443	val = port[ch].vector;
437		-#ifdef HAS_UPD7201
	444	+//#ifdef HAS_UPD7201
438	445	} else if(port[ch].pointer == 3) {
439		- val = port[ch].tx_count & 0xff;
440		- port[ch].tx_count_hi = port[ch].tx_count >> 8;
	446	+ if(__HAS_UPD7201) {
	447	+ val = port[ch].tx_count & 0xff;
	448	+ port[ch].tx_count_hi = port[ch].tx_count >> 8;
	449	+ }
441	450	} else if(port[ch].pointer == 4) {
	451	+ if(__HAS_UPD7201) {
442	452	// val = (port[ch].tx_count >> 8) & 0xff;
443		- val = port[ch].tx_count_hi;
444		-#endif
	453	+ val = port[ch].tx_count_hi;
	454	+ }
	455	+//#endif
445	456	}
446	457	port[ch].pointer = 0;
447	458	return val;

		@@ -624,24 +635,24 @@ void Z80SIO::event_callback(int event_id, int err)
624	635	if(data != port[ch].wr[6]) {
625	636	goto request_next_data;
626	637	}
627		-#ifdef SIO_DEBUG
628		- this->out_debug_log(_T("Z80SIO: ch=%d recv sync1\n"), ch);
629		-#endif
	638	+//#ifdef SIO_DEBUG
	639	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d recv sync1\n"), ch);
	640	+//#endif
630	641	port[ch].sync_bit &= ~BIT_SYNC1;
631	642	} else if(port[ch].sync_bit & BIT_SYNC2) {
632	643	if(data != port[ch].wr[7]) {
633	644	port[ch].sync_bit \|= BIT_SYNC1;
634	645	goto request_next_data;
635	646	}
636		-#ifdef SIO_DEBUG
637		- this->out_debug_log(_T("Z80SIO: ch=%d recv sync2\n"), ch);
638		-#endif
	647	+//#ifdef SIO_DEBUG
	648	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d recv sync2\n"), ch);
	649	+//#endif
639	650	port[ch].sync_bit &= ~BIT_SYNC2;
640	651	}
641	652	if(port[ch].sync_bit == 0) {
642		-#ifdef SIO_DEBUG
643		- this->out_debug_log(_T("Z80SIO: ch=%d leave hunt/sync phase\n"), ch);
644		-#endif
	653	+//#ifdef SIO_DEBUG
	654	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d leave hunt/sync phase\n"), ch);
	655	+//#endif
645	656	if(!port[ch].stat_intr) {
646	657	port[ch].stat_intr = true;
647	658	update_intr_required = true;

		@@ -655,9 +666,9 @@ void Z80SIO::event_callback(int event_id, int err)
655	666	}
656	667	}
657	668	// load received data into buffer
658		-#ifdef SIO_DEBUG
659		- this->out_debug_log(_T("Z80SIO: ch=%d recv %2x\n"), ch, data);
660		-#endif
	669	+//#ifdef SIO_DEBUG
	670	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d recv %2x\n"), ch, data);
	671	+//#endif
661	672	port[ch].recv->write(data);
662	673
663	674	// quit abort

		@@ -691,9 +702,9 @@ request_next_data:
691	702	}
692	703	if(port[ch].rtmp->empty()) {
693	704	// no data received
694		-#ifdef SIO_DEBUG
695		- this->out_debug_log(_T("Z80SIO: ch=%d end of block\n"), ch);
696		-#endif
	705	+//#ifdef SIO_DEBUG
	706	+ if(__SIO_DEBUG) this->out_debug_log(_T("Z80SIO: ch=%d end of block\n"), ch);
	707	+//#endif
697	708	port[ch].recv_id = -1;
698	709	} else {
699	710	REGISTER_RECV_EVENT(ch);

		@@ -808,36 +819,39 @@ void Z80SIO::update_intr()
808	819
809	820	// create vector
810	821	if(port[1].wr[1] & 4) {
811		-#ifdef HAS_UPD7201
812		- uint8_t affect = 7; // no interrupt pending
813		- for(int ch = 0; ch < 2; ch++) {
814		- if(port[ch].in_service) {
815		- break;
	822	+//#ifdef HAS_UPD7201
	823	+ if(__HAS_UPD7201) {
	824	+ uint8_t affect = 7; // no interrupt pending
	825	+ for(int ch = 0; ch < 2; ch++) {
	826	+ if(port[ch].in_service) {
	827	+ break;
	828	+ }
	829	+ if(port[ch].req_intr) {
	830	+ affect = port[ch].affect;
	831	+ break;
	832	+ }
816	833	}
817		- if(port[ch].req_intr) {
818		- affect = port[ch].affect;
819		- break;
	834	+ uint8_t mode = port[0].wr[2] & 0x38;
	835	+ if(mode == 0 \|\| mode == 8 \|\| mode == 0x20 \|\| mode == 0x28 \|\| mode == 0x38) {
	836	+ port[1].vector = (port[1].wr[2] & 0xe3) \| (affect << 2); // 8085
	837	+ } else {
	838	+ port[1].vector = (port[1].wr[2] & 0xf8) \| (affect << 0); // 8086
820	839	}
821		- }
822		- uint8_t mode = port[0].wr[2] & 0x38;
823		- if(mode == 0 \|\| mode == 8 \|\| mode == 0x20 \|\| mode == 0x28 \|\| mode == 0x38) {
824		- port[1].vector = (port[1].wr[2] & 0xe3) \| (affect << 2); // 8085
825	840	} else {
826		- port[1].vector = (port[1].wr[2] & 0xf8) \| (affect << 0); // 8086
827		- }
828		-#else
829		- uint8_t affect = 3; // no interrupt pending
830		- for(int ch = 0; ch < 2; ch++) {
831		- if(port[ch].in_service) {
832		- break;
833		- }
834		- if(port[ch].req_intr) {
835		- affect = port[ch].affect;
836		- break;
	841	+//#else
	842	+ uint8_t affect = 3; // no interrupt pending
	843	+ for(int ch = 0; ch < 2; ch++) {
	844	+ if(port[ch].in_service) {
	845	+ break;
	846	+ }
	847	+ if(port[ch].req_intr) {
	848	+ affect = port[ch].affect;
	849	+ break;
	850	+ }
837	851	}
	852	+ port[1].vector = (port[1].wr[2] & 0xf1) \| (affect << 1);
838	853	}
839		- port[1].vector = (port[1].wr[2] & 0xf1) \| (affect << 1);
840		-#endif
	854	+//#endif
841	855	} else {
842	856	port[1].vector = port[1].wr[2];
843	857	}

		@@ -928,10 +942,12 @@ void Z80SIO::save_state(FILEIO* state_fio)
928	942	state_fio->FputBool(port[i].abort);
929	943	state_fio->FputBool(port[i].sync);
930	944	state_fio->FputUint8(port[i].sync_bit);
931		-#ifdef HAS_UPD7201
932		- state_fio->FputUint16(port[i].tx_count);
933		- state_fio->FputUint8(port[i].tx_count_hi);
934		-#endif
	945	+//#ifdef HAS_UPD7201
	946	+ if(__HAS_UPD7201) {
	947	+ state_fio->FputUint16(port[i].tx_count);
	948	+ state_fio->FputUint8(port[i].tx_count_hi);
	949	+ }
	950	+//#endif
935	951	state_fio->FputDouble(port[i].tx_clock);
936	952	state_fio->FputDouble(port[i].tx_interval);
937	953	state_fio->FputDouble(port[i].rx_clock);

		@@ -983,10 +999,12 @@ bool Z80SIO::load_state(FILEIO* state_fio)
983	999	port[i].abort = state_fio->FgetBool();
984	1000	port[i].sync = state_fio->FgetBool();
985	1001	port[i].sync_bit = state_fio->FgetUint8();
986		-#ifdef HAS_UPD7201
987		- port[i].tx_count = state_fio->FgetUint16();
988		- port[i].tx_count_hi = state_fio->FgetUint8();
989		-#endif
	1002	+//#ifdef HAS_UPD7201
	1003	+ if(__HAS_UPD7201) {
	1004	+ port[i].tx_count = state_fio->FgetUint16();
	1005	+ port[i].tx_count_hi = state_fio->FgetUint8();
	1006	+ }
	1007	+//#endif
990	1008	port[i].tx_clock = state_fio->FgetDouble();
991	1009	port[i].tx_interval = state_fio->FgetDouble();
992	1010	port[i].rx_clock = state_fio->FgetDouble();

--- a/source/src/vm/z80sio.h

+++ b/source/src/vm/z80sio.h

		@@ -10,8 +10,8 @@
10	10	#ifndef _Z80SIO_H_
11	11	#define _Z80SIO_H_
12	12
13		-#include "vm.h"
14		-#include "../emu.h"
	13	+//#include "vm.h"
	14	+//#include "../emu.h"
15	15	#include "device.h"
16	16
17	17	#define SIG_Z80SIO_RECV_CH0 0

		@@ -49,10 +49,10 @@ private:
49	49	bool abort;
50	50	bool sync;
51	51	uint8_t sync_bit;
52		-#ifdef HAS_UPD7201
	52	+//#ifdef HAS_UPD7201
53	53	uint16_t tx_count;
54	54	uint8_t tx_count_hi;
55		-#endif
	55	+//#endif
56	56	double tx_clock, tx_interval;
57	57	double rx_clock, rx_interval;
58	58	int tx_data_bits;

		@@ -94,6 +94,9 @@ private:
94	94	DEVICE d_cpu, d_child;
95	95	bool iei, oei;
96	96	uint32_t intr_bit;
	97	+
	98	+ bool __HAS_UPD7201;
	99	+ bool __SIO_DEBUG;
97	100	void update_intr();
98	101
99	102	public:

		@@ -113,6 +116,8 @@ public:
113	116	initialize_output_signals(&port[i].outputs_rxdone);
114	117	}
115	118	d_cpu = d_child = NULL;
	119	+ __HAS_UPD7201 = false;
	120	+ __SIO_DEBUG = false;
116	121	set_device_name(_T("Z80 SIO"));
117	122	}
118	123	~Z80SIO() {}

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