Tíquete #38949

Bus master DMA not working under MorphOS

: 2019-02-09 10:33 Última Atualização: 2020-03-08 03:20

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Details

Something with via-ide is not emulated correctly. When MorphOS activates its driver and tries to read data from IDE beyond identifying the device after setting UDMA mode it fails. Maybe it's related to bus master DMA not set up correctly (MV64361 may be missing PCI outbound memory mapping?) or IRQ problem? It would help if I understood how bus master DMA is emulated in QEMU... Logs I get when this happens:

PCI ATA/ATAPI Driver-Driver_SetFeature@2: done
PCI ATA/ATAPI Driver@2: UDMA Mode 5
mv64361_write: c78 <- 80006151
pci_host_data: pci_host_config_write addr 0000000000000000 len 4 val 80006151
mv64361_write: c7d <- e0
pci_host_data: write addr 0000000000000001 len 1 val e0
pci_host_data: pci_data_write: via-ide: addr=51 val=000000e0 len=1
3281@1547592409.855804:pci_cfg_write via-ide 12:1 @0x51 <- 0xe0
3281@1547592409.858572:bmdma_read_via bmdma: readb 0x2 : 0x20
3281@1547592409.858586:bmdma_write_via bmdma: writeb 0x2 : 0x26
PCI ATA/ATAPI Driver-Driver_SetParam@2: CDROM..Set no WriteCache
PCI ATA/ATAPI Driver-Driver_SetParam@2: Cylinders 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Heads 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Sectors/Cyl 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: TotalSectors 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: TotalSectors48 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Support.Flags 0x200003
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify UnitID 3
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify Try 0
PCI ATA/ATAPI Driver-Driver_Identify@3:
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
PCI ATA/ATAPI Driver-Driver_Identify@3: Status 0x0
PCI ATA/ATAPI Driver-Driver_Identify@3: ATA
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
Unassigned mem read 0000000000000080
PCI ATA/ATAPI Driver-Driver_Identify@3: Status 0x0
PCI ATA/ATAPI Driver-Driver_Identify@3: No DRQ set..no data..failed
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify failed
then similar to Try 0 above for:
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify Try 1 to Try 4
and finally:
PCI ATA/ATAPI Driver-Driver_Identify@3: Status 0x0
PCI ATA/ATAPI Driver-Driver_Identify@3: No DRQ set..no data..failed
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify failed
PCI ATA/ATAPI Driver-Driver_ScanBus@1: too many loops..set IDEUNITTYPE_UNKNOWN
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Enable Ints
What is the unimplemented register @0x80 and which device is it part of?

Ticket History (3/11 Histories)

2019-02-09 10:33 Updated by: balaton
  • New Ticket "Bus master DMA not working under MorphOS" created
2019-02-09 10:34 Updated by: balaton
  • Details Updated
2019-02-09 10:36 Updated by: balaton
  • Details Updated
2019-02-09 10:36 Updated by: balaton
  • Tipo Update from Bugs to Issues
2019-02-09 10:38 Updated by: balaton
  • Details Updated
2019-02-09 10:38 Updated by: balaton
  • Details Updated
2019-06-08 20:01 Updated by: balaton
Comentário

I could reproduce similar (same?) problem with the MIPS fulong2e board emulation as well so maybe it's not related to MV64361 but missing something in via-ide or both board emulations have the same problem with PCI windows? More details here: https://lists.nongnu.org/archive/html/qemu-devel/2019-03/msg05663.html

Unfortunately I still don't understand BMDMA emulation in QEMU so can't tell what's wrong.

(Edited, 2019-06-08 20:07 Updated by: balaton)
2020-02-08 04:26 Updated by: balaton
Comentário

After implementing the IRQ controller part of the Marvell chip, Linux now can use BMDMA and boots but MorphOS is still not happy with it and shows the same problem as above. Additional info on the logs:

The

PCI ATA/ATAPI Driver-Driver_Identify@3: Status 0x0
PCI ATA/ATAPI Driver-Driver_Identify@3: ATA
PCI ATA/ATAPI Driver-Driver_Identify@3: Status 0x0
PCI ATA/ATAPI Driver-Driver_Identify@3: No DRQ set..no data..failed
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify failed
messages seem to be a red herring and because for some reason it thinks there's an ATA slave device on ide bus 1 (note the @3 which is the unit number, starting from 0 for primary master) and tries to probe that but eventually figures out it does not exist so these may be harmless. The CD drive on secondary master (ide1 unit 0 or @2 for MorphOS) is correctly identified (still in PIO mode). It works while used in PIO mode, only fails after switched to BMDMA (while Linux does not have this problem and can use the drive in DMA mode):
PCI ATA/ATAPI Driver-Driver_Identify@2: Status 0x50
PCI ATA/ATAPI Driver-Driver_Identify@2: no error
...
PCI ATA/ATAPI Driver-Driver_DumpIdentifyATAPI: atap_model[20]=<QEMU DVD-ROM                            >
...
PCI ATA/ATAPI Driver-Driver_Identify@2: Result 0x1
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Identify succeed
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Signature 0x0
PCI ATA/ATAPI Driver-Driver_ScanBus@1: Config 0x85c0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Type 0x4
PCI ATA/ATAPI Driver-Driver_SetParam@2: Capabilities 0x300
PCI ATA/ATAPI Driver-Driver_SetParam@2: PIOMode 0x0
PCI ATA/ATAPI Driver-Driver_SetParam@2: ATAPI supports at least PioMode 3
PCI ATA/ATAPI Driver-Driver_SetParam@2: Old PIOMode 0x3 DMAMode 0x0
PCI ATA/ATAPI Driver-Driver_SetParam@2: New PIOMode/DMAMode fields are valid
PCI ATA/ATAPI Driver-Driver_SetParam@2: PIOMask 0x3 DMAMask 0x7
PCI ATA/ATAPI Driver-Driver_SetParam@2: Supported PIOMode 4 DMAMode 2 UDMAMode 5
PCI ATA/ATAPI Driver-Driver_SetParam@2: Version 30 Revision 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: 12 byte cmds
PCI ATA/ATAPI Driver-Driver_SetParam@2: Max PIOMode 4
PCI ATA/ATAPI Driver-Driver_SetParam@2: Set PioMode 4
PCI ATA/ATAPI Driver-Driver_SetFeature@2: Code 0x3 SubCode 0xc
[some reads of port 0x80]
PCI ATA/ATAPI Driver-Driver_SetFeature@2: done
PCI ATA/ATAPI Driver@2: PIO Mode 4
write VT8231 IDE reg 0x49 <- 20
PCI ATA/ATAPI Driver-Driver_SetParam@2: Set DmaMode 2
PCI ATA/ATAPI Driver-Driver_SetFeature@2: Code 0x3 SubCode 0x22
[some reads of port 0x80]
PCI ATA/ATAPI Driver-Driver_SetFeature@2: done
12175@1581099914.306435:bmdma_read_via bmdma: readb 0x2 : 0x00
12175@1581099914.306451:bmdma_write_via bmdma: writeb 0x2 : 0x26
PCI ATA/ATAPI Driver-Driver_SetParam@2: Set UDmaMode 5
PCI ATA/ATAPI Driver-Driver_SetFeature@2: Code 0x3 SubCode 0x45
[some reads of port 0x80]
PCI ATA/ATAPI Driver-Driver_SetFeature@2: done
PCI ATA/ATAPI Driver@2: UDMA Mode 5
write VT8231 IDE reg 0x51 <- e0
12175@1581099914.307054:bmdma_read_via bmdma: readb 0x2 : 0x20
12175@1581099914.307057:bmdma_write_via bmdma: writeb 0x2 : 0x26
PCI ATA/ATAPI Driver-Driver_SetParam@2: CDROM..Set no WriteCache
PCI ATA/ATAPI Driver-Driver_SetParam@2: Cylinders 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Heads 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Sectors/Cyl 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: TotalSectors 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: TotalSectors48 0
PCI ATA/ATAPI Driver-Driver_SetParam@2: Support.Flags 0x200003
After this setup the driver is started and tries to access devices now in bus master DMA mode:
Dev_Inquiry@ide.device-0: DiskPort 0x140e60b0
Dev_Inquiry@ide.device-0: NextLun(Can`t open device)
Dev_Inquiry@ide.device-1: DiskPort 0x140e60b0
Dev_Inquiry@ide.device-1: NextLun(Can`t open device)
Dev_Inquiry@ide.device-2: DiskPort 0x140e60b0
Dev_Inquiry@ide.device-2: ATAPI
Dev_InquirySCSI@ide.device-2:
Dev_InquirySCSI@ide.device-2: Send TestDrive
[some reads of port 0x80]
12175@1581099914.316212:ide_atapi_cmd IDEState: 0x55dd9fb34c78; cmd: 0x00
12175@1581099914.316216:ide_atapi_cmd_packet IDEState: 0x55dd9fb34c78; limit=0x8000 packet: 00 00 00 00 00 00 00 00 00 00 00 00
There are no devices on primary ide bus so the "Can't open device" errors are because of that, then tries to send a TEST UNIT READY command to the CD drive on secondary master which does reach the drive emulation but the response never arrives and it freezes here presumably waiting for this command to return. IRQs seem to be raised and lowered but it may be due to other sources so don't know if it's waiting for an IRQ from BMDMA or something else is amiss. During early startup when setting up the PIC MorphOS tries to set level sensitive interrupts which are logged as not supported:
i8259: level sensitive irq not supported
i8259: level sensitive irq not supported
which Linux does not seem to do so this may be related but this seems to only cause problem with BMDMA but PIO works so not sure it's because that does not use IRQ or something else or this is not related to the problem.

The Unassigned mem read to address 0x80 seems to be accessing an undocumented debug port of VT8231 at io port 0x80 which is done after every IDE command or IRQ a few times but I don't know what it's looking for there or if it's only accessed in error instead of something else due to some register returning 0 earlier instead of an address of which offset 0x80 is meant to be read here.

(Edited, 2020-02-08 04:28 Updated by: balaton)
2020-02-11 06:40 Updated by: balaton
Comentário

I could also reproduce it with AmigaOS4 now, here are some detailed debug logs with more QEMU logging enabled. This is with two ide controllers: the default via-ide and an sii3112 PCI SATA added, both having only an ide-cd connected, no harddisks. On via-ide the CD is secondary master and the sii3112 has another ide-cd on port 0 with port 1 empty. So everything is the same for the two controllers except the interrupt routing. AmigaOS4 finds both cd drives but fails to access them after enabling BMDMA.

peg2ide.device 53.3 (05.02.2009)
#testing for devices on first port:
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f8307e0
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x06; bus 0x55d73f8307e0
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f8307e0
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8307e0 IDEState 0x55d73f830868
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f8307e0 IDEState 0x55d73f830c38

#nothing found, testing second port where ide-cd is master:
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f8310d0
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x55; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x06; bus 0x55d73f8310d0
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f8310d0
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x4 (Cylinder Low); val 0x14; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x5 (Cylinder High); val 0xeb; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x01; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x4 (Cylinder Low); val 0xff; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x5 (Cylinder High); val 0xff; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x10; bus 0x55d73f8310d0 IDEState 0x55d73f831528
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831528
# enabling bus master DMA then trying to identify device:
bmdma_addr_write data: 0x0000000002290000
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x00; bus 0x55d73f8310d0
ide_ioport_write IDE PIO wr @ 0x1 (Features); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x4 (Cylinder Low); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x5 (Cylinder High); val 0x00; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x40; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_ioport_write IDE PIO wr @ 0x7 (Command); val 0xa1; bus 0x55d73f8310d0 IDEState 0x55d73f831158
ide_exec_cmd IDE exec cmd: bus 0x55d73f8310d0; state 0x55d73f831158; cmd 0xa1
# an IRQ is expected here that never arrives
[peg2ide/irq_wait] timed out
[peg2ide/exec_pio_data_in_cmd] <- here
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x58; bus 0x55d73f8310d0 IDEState 0x55d73f831158
[peg2ide/ata_read_drive_properties] unit 2 returned error 255, failbits 00000000h, timeout 0
[peg2ide/ata_read_drive_properties] After-reset signature invalid for unit 3

# start driver for other controller:
sii3112ide.device 53.3 (05.02.2009)
sii3112_write bmdma: write (size 1) 0x8a : 0x02
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f9c9460
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x82 : 0x55
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x83 : 0xaa
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x82 : 0xaa
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x83 : 0x55
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x82 : 0x55
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x83 : 0xaa
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x55; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x82 : 0x55
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x83 : 0xaa
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x8a : 0x06
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x06; bus 0x55d73f9c9460
sii3112_write bmdma: write (size 1) 0x8a : 0x02
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f9c9460
sii3112_set_irq channel 0 level 0
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x87 : 0x00
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x01; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x82 : 0x01
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x01; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x83 : 0x01
ide_ioport_read IDE PIO rd @ 0x4 (Cylinder Low); val 0x14; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x84 : 0x14
ide_ioport_read IDE PIO rd @ 0x5 (Cylinder High); val 0xeb; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x85 : 0xeb
sii3112_set_irq channel 0 level 0
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x87 : 0x00
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 4) 0x4 : 0x22c0000
#found ide-cd on port 0, enabling BMDMA
bmdma_addr_write data: 0x00000000022c0000
# here it installs IRQ handler for sii3112 but at this point an interrupt for via=ide arrives?
mv64361_gpp_irq(0x55d73f635750, 31, 1) levels=80000000 mask=80000000
mv64361_update_irq(0x55d73f635750, 59, 1)
mv64361_gpp_irq(0x55d73f635750, 31, 0) levels=0
mv64361_update_irq(0x55d73f635750, 59, 0)

# the next unassigned read is accessing sii3112state.regs[0].confstat but unalligned which is not supported by emulation but it continues nevertheless, maybe checking for some unexpected state but getting 0 reply is fine and moves on to identifying device:
Unassigned mem read 00000000810040a1
sii3112_write bmdma: write (size 1) 0x86 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_set_irq channel 0 level 0
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x87 : 0x00
sii3112_write bmdma: write (size 1) 0x8a : 0x00
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x00; bus 0x55d73f9c9460
sii3112_write bmdma: write (size 1) 0x81 : 0x00
ide_ioport_write IDE PIO wr @ 0x1 (Features); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x82 : 0x00
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x83 : 0x00
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x84 : 0x00
ide_ioport_write IDE PIO wr @ 0x4 (Cylinder Low); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x85 : 0x00
ide_ioport_write IDE PIO wr @ 0x5 (Cylinder High); val 0x00; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x86 : 0x40
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x40; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_write bmdma: write (size 1) 0x87 : 0xa1
ide_ioport_write IDE PIO wr @ 0x7 (Command); val 0xa1; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
ide_exec_cmd IDE exec cmd: bus 0x55d73f9c9460; state 0x55d73f9c94e8; cmd 0xa1
# waits for IRQ here which seems to be generated and comes in the right gpio pin but isn't delivered to CPU because corresponding mask bit is not set for some reason? Still only irq for via-ide seems to be enabled.
sii3112_set_irq channel 0 level 1
mv64361_pcihost_set_irq(0x55d73f6363b0, 1, 1)
mv64361_gpp_irq(0x55d73f635750, 13, 1) levels=2000 mask=80000000
[sii3112ide/irq_wait] timed out
[sii3112ide/exec_pio_data_in_cmd] <- here
sii3112_set_irq channel 0 level 0
mv64361_pcihost_set_irq(0x55d73f6363b0, 1, 0)
mv64361_gpp_irq(0x55d73f635750, 13, 0) levels=0
mv64361_update_irq(0x55d73f635750, 57, 0)
ide_ioport_read IDE PIO rd @ 0x7 (Status); val 0x58; bus 0x55d73f9c9460 IDEState 0x55d73f9c94e8
sii3112_read bmdma: read (size 1) 0x87 : 0x58
[sii3112ide/ata_read_drive_properties] unit 0 returned error 255, failbits 00000000h, timeout 0

# trying port 1 but there's no device connected there:
sii3112_write bmdma: write (size 1) 0xca : 0x02
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f9c9d50
sii3112_write bmdma: write (size 1) 0xc6 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc2 : 0x55
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc3 : 0xaa
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc2 : 0xaa
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0xaa; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc3 : 0x55
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0x55; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc2 : 0x55
ide_ioport_write IDE PIO wr @ 0x2 (Sector Count); val 0x55; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc3 : 0xaa
ide_ioport_write IDE PIO wr @ 0x3 (Sector Number); val 0xaa; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_read bmdma: read (size 1) 0xc2 : 0x00
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_read bmdma: read (size 1) 0xc3 : 0x00
sii3112_write bmdma: write (size 1) 0xc6 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xca : 0x06
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x06; bus 0x55d73f9c9d50
sii3112_write bmdma: write (size 1) 0xca : 0x02
ide_cmd_write IDE PIO wr @ 0x4 (Device Control); val 0x02; bus 0x55d73f9c9d50
sii3112_write bmdma: write (size 1) 0xc6 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_write bmdma: write (size 1) 0xc6 : 0x00
ide_ioport_write IDE PIO wr @ 0x6 (Device/Head); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
ide_ioport_read IDE PIO rd @ 0x2 (Sector Count); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_read bmdma: read (size 1) 0xc2 : 0x00
ide_ioport_read IDE PIO rd @ 0x3 (Sector Number); val 0x00; bus 0x55d73f9c9d50 IDEState 0x55d73f9c9dd8
sii3112_read bmdma: read (size 1) 0xc3 : 0x00
2020-03-08 03:19 Updated by: balaton
Comentário

Implementing IRQ routing in pegasos2 and fixing via-ide IRQ handling to match hardware fixed this. Patches submitted to QEMU: http://patchwork.ozlabs.org/project/qemu-devel/list/?series=161714

2020-03-08 03:20 Updated by: balaton
  • Estado Update from Aberto to Fechado

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