SIMD instruction generation (Coins-compiler-users) - COINS Compiler Infrastructure

Hi, Daniel,

You can find examples of TMD expressions for parallel instructions in
   lines 605-679 of coins/backend/gen/x86.tmd .

For example,

(defrule void (PARALLEL
	       (SET I64
		    (MEM I64 (SUB I32 (REG I32 "%esp") (INTCONST I32 8)))
		    mrcq)
	       (SET I32
		    (REG I32 "%esp")
		    (SUB I32 (REG I32 "%esp") (INTCONST I32 8))))
   (code (pushl (qhigh $1))
	(pushl (qlow $1)))
   (cost 2))

Ikuo Nakata

On 2009/06/15, at 5:46, Daniel Shapiro wrote:

> Thanks Tan,
>
> I am curious how the parallel instruction can be used in instruction  
> selection. I have 2 questions:
>
> Question 1:
>
> Assuming proper syntax, will the LIR expression (PARALLEL (SET A = B 
> +C), (SET D = E + F)) be emitted as 2 instructions? Is there a TMD  
> expression and corresponding java rule to force this parallel  
> instruction to be emitted as the following assembly:
>
> padd a,d, b,c,e,f;
>
> Also, the order of a,d, b,c,e,f is important and must be  
> deterministic.
>
> Question 2:
>
> Is there a way to build an instruction where 4 inputs feed 2 outputs?
>
> Example:
>
> parallel
> ((set output1=x+b+c),
> (set output2=y+b+c))
>
> I am trying to emit an instruction
>
> padd output1,output2, x,y,b,c;
>
> And again, the order of output1,output2, x,y,b,c is important and  
> must be deterministic.
>
> Thank you for your help in understanding the backend,
>
> -Daniel
>
> 2009/6/14 Tan Watanabe <tan****@watan*****>
> Hi, Daniel,
>
>
> At 23:58 09/06/09, you wrote:
> p.s. I have a quick question:
>
> can I have instructions in TMD that have more than 2 input registers?
>
> also
>
> can I have instructions in TMD that have more than 1 output register?
>
> The LIR epxression
>
>    (PARALLEL  x1, x2, ... xn)
>
> may have more than 2 input registers when it contains more than 1  
> subexpression.
> It may have also more than 1 output registers when it contains more  
> than 1
> SET expression.
>
> The LIR expression
>
>    (CALL x1 (x2…xn) (y1…ym))
>
> may also have more than 2 input registers and more than 1 output  
> registers
> but it is used to call a subprogram.
>
>
> Thanks,
>
>
> --
> Daniel Shapiro, <http://B.A.Sc>B.A.Sc ., <http://M.A.Sc>M.A.Sc.,  
> Ph.D. (Candidate)
>
> Tan Watanabe <tan****@watan*****>
>
>
>
> -- 
> Daniel Shapiro, B.A.Sc ., M.A.Sc., Ph.D. (Candidate)
>
> School of Information Technology and Engineering (SITE), University  
> of Ottawa
> Tel: (613) 562-5800 ext. 2192
> Office: SITE4009C
> Email: dshap092 -at- site.uottawa.ca
> Website: site.uottawa.ca/~dshap092/
> Research Group: carg.site.uottawa.ca/
> _______________________________________________
> Coins-compiler-users mailing list
> Coins****@lists*****
> http://lists.sourceforge.jp/mailman/listinfo/coins-compiler-users

中田 育男
nakat****@kamak*****

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[Coins-compiler-users] SIMD instruction generation