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hardware/intel/intel-driver


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Revisão32de8cf8314d6ae2377230f9863078de0e9a3635 (tree)
Hora2014-11-11 19:57:19
AutorGwenole Beauchesne <gwenole.beauchesne@inte...>
CommiterGwenole Beauchesne

Mensagem de Log

vpp: enable advanced video scaling in VPP pipelines too.

Honour advanced video scaling. i.e. propagate vaPutSurface() scaling
flags, but also VPP filter flags. Also enable the sharp 8x8 filter for
high-quality scaling options, while adaptive video scaling is disabled
(bypassed) for now.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Mudança Sumário

Diff

--- a/src/gen75_vpp_vebox.c
+++ b/src/gen75_vpp_vebox.c
@@ -1236,12 +1236,13 @@ int hsw_veb_post_format_convert(VADriverContextP ctx,
12361236 vpp_surface_convert(ctx, obj_surface, proc_ctx->surface_output_object);
12371237
12381238 } else if(proc_ctx->format_convert_flags & POST_SCALING_CONVERT) {
1239+ VAProcPipelineParameterBuffer * const pipe = proc_ctx->pipeline_param;
12391240 /* scaling, convert and copy NV12 to YV12/IMC3/IMC2/RGBA output*/
12401241 assert(obj_surface->fourcc == VA_FOURCC_NV12);
12411242
12421243 /* first step :surface scaling */
12431244 vpp_surface_scaling(ctx, obj_surface,
1244- proc_ctx->surface_output_scaled_object, 0);
1245+ proc_ctx->surface_output_scaled_object, pipe->filter_flags);
12451246
12461247 /* second step: color format convert and copy to output */
12471248 obj_surface = proc_ctx->surface_output_object;
--- a/src/gen8_post_processing.c
+++ b/src/gen8_post_processing.c
@@ -895,7 +895,7 @@ gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con
895895
896896 sx = (float)dst_rect->width / src_rect->width;
897897 sy = (float)dst_rect->height / src_rect->height;
898- avs_update_coefficients(avs, sx, sy, 0);
898+ avs_update_coefficients(avs, sx, sy, pp_context->filter_flags);
899899
900900 assert(avs->config->num_phases == 16);
901901 for (i = 0; i <= 16; i++) {
@@ -962,7 +962,8 @@ gen8_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con
962962 intel_format_convert(coeffs->uv_k_v[3], 1, 6, 1);
963963 }
964964
965- sampler_8x8->dw152.default_sharpness_level = 0;
965+ sampler_8x8->dw152.default_sharpness_level =
966+ -avs_is_needed(pp_context->filter_flags);
966967 sampler_8x8->dw153.adaptive_filter_for_all_channel = 1;
967968 sampler_8x8->dw153.bypass_y_adaptive_filtering = 1;
968969 sampler_8x8->dw153.bypass_x_adaptive_filtering = 1;
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -2483,7 +2483,7 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context
24832483
24842484 sx = (float)dst_rect->width / src_rect->width;
24852485 sy = (float)dst_rect->height / src_rect->height;
2486- avs_update_coefficients(avs, sx, sy, 0);
2486+ avs_update_coefficients(avs, sx, sy, pp_context->filter_flags);
24872487
24882488 assert(avs->config->num_phases == 16);
24892489 for (i = 0; i <= 16; i++) {
@@ -2545,7 +2545,8 @@ pp_nv12_avs_initialize(VADriverContextP ctx, struct i965_post_processing_context
25452545 /* Adaptive filter for all channels (DW4.15) */
25462546 sampler_8x8_state->coefficients[0].dw4.table_1x_filter_c1 = 1U << 7;
25472547
2548- sampler_8x8_state->dw136.default_sharpness_level = 0;
2548+ sampler_8x8_state->dw136.default_sharpness_level =
2549+ -avs_is_needed(pp_context->filter_flags);
25492550 sampler_8x8_state->dw137.ilk.bypass_y_adaptive_filtering = 1;
25502551 sampler_8x8_state->dw137.ilk.bypass_x_adaptive_filtering = 1;
25512552 dri_bo_unmap(pp_context->sampler_state_table.bo_8x8);
@@ -2838,7 +2839,7 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con
28382839
28392840 sx = (float)dst_rect->width / src_rect->width;
28402841 sy = (float)dst_rect->height / src_rect->height;
2841- avs_update_coefficients(avs, sx, sy, 0);
2842+ avs_update_coefficients(avs, sx, sy, pp_context->filter_flags);
28422843
28432844 assert(avs->config->num_phases == 16);
28442845 for (i = 0; i <= 16; i++) {
@@ -2897,7 +2898,8 @@ gen7_pp_plx_avs_initialize(VADriverContextP ctx, struct i965_post_processing_con
28972898 intel_format_convert(coeffs->uv_k_v[3], 1, 6, 1);
28982899 }
28992900
2900- sampler_8x8_state->dw136.default_sharpness_level = 0;
2901+ sampler_8x8_state->dw136.default_sharpness_level =
2902+ -avs_is_needed(pp_context->filter_flags);
29012903 if (IS_HASWELL(i965->intel.device_info)) {
29022904 sampler_8x8_state->dw137.hsw.adaptive_filter_for_all_channel = 1;
29032905 sampler_8x8_state->dw137.hsw.bypass_y_adaptive_filtering = 1;
@@ -4809,6 +4811,8 @@ i965_scaling_processing(
48094811 if (HAS_VPP(i965)) {
48104812 struct i965_surface src_surface;
48114813 struct i965_surface dst_surface;
4814+ struct i965_post_processing_context *pp_context;
4815+ unsigned int filter_flags;
48124816
48134817 _i965LockMutex(&i965->pp_mutex);
48144818
@@ -4819,10 +4823,16 @@ i965_scaling_processing(
48194823 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
48204824 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
48214825
4822- va_status = i965_post_processing_internal(ctx, i965->pp_context,
4826+ pp_context = i965->pp_context;
4827+ filter_flags = pp_context->filter_flags;
4828+ pp_context->filter_flags = va_flags;
4829+
4830+ va_status = i965_post_processing_internal(ctx, pp_context,
48234831 &src_surface, src_rect, &dst_surface, dst_rect,
48244832 avs_is_needed(va_flags) ? PP_NV12_AVS : PP_NV12_SCALING, NULL);
48254833
4834+ pp_context->filter_flags = filter_flags;
4835+
48264836 _i965UnlockMutex(&i965->pp_mutex);
48274837 }
48284838
@@ -4849,6 +4859,7 @@ i965_post_processing(
48494859 VAStatus status;
48504860 struct i965_surface src_surface;
48514861 struct i965_surface dst_surface;
4862+ struct i965_post_processing_context *pp_context;
48524863
48534864 /* Currently only support post processing for NV12 surface */
48544865 if (obj_surface->fourcc != VA_FOURCC_NV12)
@@ -4856,6 +4867,8 @@ i965_post_processing(
48564867
48574868 _i965LockMutex(&i965->pp_mutex);
48584869
4870+ pp_context = i965->pp_context;
4871+ pp_context->filter_flags = va_flags;
48594872 if (avs_is_needed(va_flags)) {
48604873 struct i965_render_state *render_state = &i965->render_state;
48614874 struct intel_region *dest_region = render_state->draw_region;
@@ -4877,13 +4890,13 @@ i965_post_processing(
48774890 obj_surface = SURFACE(out_surface_id);
48784891 assert(obj_surface);
48794892 i965_check_alloc_surface_bo(ctx, obj_surface, 0, VA_FOURCC_NV12, SUBSAMPLE_YUV420);
4880- i965_vpp_clear_surface(ctx, i965->pp_context, obj_surface, 0);
4893+ i965_vpp_clear_surface(ctx, pp_context, obj_surface, 0);
48814894
48824895 dst_surface.base = (struct object_base *)obj_surface;
48834896 dst_surface.type = I965_SURFACE_TYPE_SURFACE;
48844897 dst_surface.flags = I965_SURFACE_FLAG_FRAME;
48854898
4886- i965_post_processing_internal(ctx, i965->pp_context,
4899+ i965_post_processing_internal(ctx, pp_context,
48874900 &src_surface,
48884901 src_rect,
48894902 &dst_surface,
@@ -5652,6 +5665,7 @@ i965_proc_picture(VADriverContextP ctx,
56525665 NULL);
56535666 } else {
56545667
5668+ proc_context->pp_context.filter_flags = pipeline_param->filter_flags;
56555669 i965_post_processing_internal(ctx, &proc_context->pp_context,
56565670 &src_surface,
56575671 &src_rect,
--- a/src/i965_post_processing.h
+++ b/src/i965_post_processing.h
@@ -491,6 +491,15 @@ struct i965_post_processing_context
491491 struct pp_dn_context pp_dn_context;
492492 void *private_context; /* pointer to the current private context */
493493 void *pipeline_param; /* pointer to the pipeline parameter */
494+ /**
495+ * \ref Extra filter flags used as a fast path.
496+ *
497+ * This corresponds to vaPutSurface() flags, for direct rendering,
498+ * or to VAProcPipelineParameterBuffer.filter_flags when the VPP
499+ * interfaces are used. In the latter case, this is just a copy of
500+ * that field.
501+ */
502+ unsigned int filter_flags;
494503
495504 int (*pp_x_steps)(void *private_context);
496505 int (*pp_y_steps)(void *private_context);