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Motorola M6800 (6800) Exorciser / SWTPC emulator plus 6801 instruction set emulation


Commit MetaInfo

Revisãocc0e06aeb3c9272f68b0f27a7df1e37ab9de3c85 (tree)
Hora2020-11-22 17:23:23
AutorJoel Matthew Rees <joel.rees@gmai...>
CommiterJoel Matthew Rees

Mensagem de Log

unasm changed to runtime option for 6801, lightly tested, forgotten
exorsim.c added

Mudança Sumário

Diff

--- a/asm6800.c
+++ b/asm6800.c
@@ -192,9 +192,9 @@ enum {
192192 ACC, /* Accumulator needed */
193193 ACC1, /* Accumulator optional */
194194 ACCB, /* we need an A or a B: add 0x01 for B */
195-#ifdef SIM6801
195+/* #ifdef SIM6801 */
196196 ACCD, /* LDD,STD,ADDD,SUBD */
197-#endif /* def SIM6801 */
197+/* #endif / * def SIM6801 */
198198 NONE /* No operand */
199199 };
200200
--- /dev/null
+++ b/exorsim.c
@@ -0,0 +1,28 @@
1+/* Configurations file
2+ * for modifications to Joseph H. Allen's Exorsim
3+ * This file copyright 2020 Joel Matthew Rees
4+ *
5+ * This is free software; you can redistribute it and/or modify it under the
6+ * terms of the GNU General Public License as published by the Free Software
7+ * Foundation; either version 1, or (at your option) any later version.
8+ *
9+ * It is distributed in the hope that it will be useful, but WITHOUT ANY
10+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
11+ * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
12+ * details.
13+ *
14+ * You should have received a copy of the GNU General Public License along with
15+ * this software; see the file COPYING. If not, write to the Free Software Foundation,
16+ * 675 Mass Ave, Cambridge, MA 02139, USA.
17+ */
18+
19+
20+#define EXORSIM_C
21+
22+#include "exorsim.h"
23+
24+unsigned cputype = SIM6801;
25+
26+
27+
28+
--- a/sim6800.c
+++ b/sim6800.c
@@ -258,11 +258,11 @@ void show_trace(int insn_no, struct trace_entry *t)
258258 } case 0x02: /* SBC N,Z,V,C (no H?) */ {
259259 insn = "SBC";
260260 break;
261- } case 0x03: /* ACCMD should never get here at run time? */ {
261+ } case 0x03: /* ACCMD should never get here at run time when CPU is 6801? */ {
262262 if (cputype == 0x6800)
263263 goto invalid; /* ??? */
264264 else
265- insn = "SUBD***";
265+ insn = "???SUBD";
266266 break;
267267 } case 0x04: /* AND N,Z,V=0 */ {
268268 insn = "AND";
@@ -349,31 +349,31 @@ void show_trace(int insn_no, struct trace_entry *t)
349349 insn = "STS";
350350 break;
351351 } case 0x9D: case 0xAD: case 0xBD: /* JSR */ {
352- if (cputype == 0x6800 && t->insn[0] == 0x9D)
353-{ fputs( "JSR error\n", stderr ); goto invalid16;
354-} else if (t->cc & 0x80)
352+ if (cputype < 0x6801 && t->insn[0] == 0x9D)
353+ goto invalid16;
354+ else if (t->cc & 0x80)
355355 sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
356356 insn = "JSR";
357357 subr = 1;
358358 break;
359359 } case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
360- if (cputype == 0x6800)
361-{ fputs( "ADDD error\n", stderr ); goto invalid16;
362-} else if (t->cc & 0x80)
360+ if (cputype < 0x6801)
361+ goto invalid16;
362+ else if (t->cc & 0x80)
363363 sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
364364 insn = "ADDD";
365365 break;
366366 } case 0xCC: case 0xDC: case 0xEC: case 0xFC: /* LDD N,Z,V=0 (6801) */ {
367- if (cputype == 0x6800)
368-{ fputs( "LDD error\n", stderr ); goto invalid16;
369-} else if (t->cc & 0x80)
367+ if (cputype < 0x6801)
368+ goto invalid16;
369+ else if (t->cc & 0x80)
370370 sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
371371 insn = "LDD";
372372 break;
373373 } case 0xCD: case 0xDD: case 0xED: case 0xFD: /* STD N,Z,V=0 (6801) */ {
374- if (cputype == 0x6800)
375-{ fputs( "STD error\n", stderr ); goto invalid16;
376-} else if (t->cc & 0x80)
374+ if (cputype < 0x6801)
375+ goto invalid16;
376+ else if (t->cc & 0x80)
377377 sprintf(buf3, "EA=%4.4X%s D=%4.4X", t->ea, buf_ea, t->data);
378378 insn = "STD";
379379 break;
@@ -389,7 +389,6 @@ void show_trace(int insn_no, struct trace_entry *t)
389389 break;
390390 } default: /* ??? */ {
391391 invalid16:
392-fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
393392 goto invalid;
394393 break;
395394 }
@@ -475,16 +474,14 @@ fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
475474 insn = "NOP";
476475 break;
477476 } case 0x04: /* LSRD N=0,Z,V,C (6801) */ {
478- if (cputype == 0x6800)
477+ if (cputype < 0x6801)
479478 goto invalidinh;
480- else
481- insn = "LSRD";
479+ insn = "LSRD";
482480 break;
483481 } case 0x05: /* LSLD N,Z,V,C (6801) */ {
484- if (cputype == 0x6800)
482+ if (cputype < 0x6801)
485483 goto invalidinh;
486- else
487- insn = "LSLD";
484+ insn = "LSLD";
488485 break;
489486 } case 0x06: /* TAP (all flags) */ {
490487 insn = "TAP";
@@ -542,15 +539,13 @@ fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
542539 insn = "BRA";
543540 break;
544541 } case 0x21: /* BRN (6801) */ {
545- if (cputype == 0x6800)
542+ if (cputype < 0x6801)
546543 goto invalidinh;
547- else {
548- sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
549- sprintf(operand, " %4.4X", t->pc + 2 + (char)t->insn[1]);
550- if (t->cc & 0x80)
551- sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
552- insn = "BRN";
553- }
544+ sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
545+ sprintf(operand, " %4.4X", t->pc + 2 + (char)t->insn[1]);
546+ if (t->cc & 0x80)
547+ sprintf(buf3, "EA=%4.4X%s", t->ea, buf_ea);
548+ insn = "BRN";
554549 break;
555550 } case 0x22: /* BHI */ {
556551 sprintf(buf + strlen(buf), "%2.2X ", t->insn[1]);
@@ -675,7 +670,7 @@ fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
675670 insn = "PSHB";
676671 break;
677672 } case 0x38: /* PULX (6801) */ {
678- if (cputype == 0x6800)
673+ if (cputype < 0x6801)
679674 goto invalidinh;
680675 else
681676 insn = "PULX";
@@ -685,26 +680,23 @@ fprintf( stderr, "invalid16 from mnemonic: %x\n", t->insn[0] );
685680 subr = 1;
686681 break;
687682 } case 0x3A: /* ABX (6801) */ {
688- if (cputype == 0x6800)
683+ if (cputype < 0x6801)
689684 goto invalidinh;
690- else
691- insn = "ABX";
685+ insn = "ABX";
692686 break;
693687 } case 0x3B: /* RTI */ {
694688 insn = "RTI";
695689 subr = 1;
696690 break;
697691 } case 0x3C: /* PSHX (6801) */ {
698- if (cputype == 0x6800)
692+ if (cputype < 0x6801)
699693 goto invalidinh;
700- else
701- insn = "PSHX";
694+ insn = "PSHX";
702695 break;
703696 } case 0x3D: /* MUL C=accb bit 7 (6801) */ {
704- if (cputype == 0x6800)
697+ if (cputype < 0x6801)
705698 goto invalidinh;
706- else
707- insn = "MUL";
699+ insn = "MUL";
708700 break;
709701 } case 0x3E: /* WAI */ {
710702 insn = "WAI";
@@ -997,7 +989,7 @@ void sim(void)
997989 }
998990 switch (opcode) {
999991 case 0x83: case 0x93: case 0xA3: case 0xB3: /* SUBD N,Z,V,C (6801) */ {
1000- if (cputype == 0x6800) {
992+ if (cputype < 0x6801) {
1001993 fprintf( stderr, "Internal error on SUBD (6800)\n" );
1002994 goto invalid16;
1003995 }
@@ -1018,7 +1010,7 @@ void sim(void)
10181010 t->ea = ea; t->data = w;
10191011 fw = ix - w;
10201012 z_flag = Z_16(fw);
1021- if (cputype == 0x6800) {
1013+ if (cputype < 0x6801) {
10221014 f = ( ix >> 8 ) - ( w >> 8 );
10231015 n_flag = N(f);
10241016 v_flag = V(ix >> 8, w >> 8, f);
@@ -1048,18 +1040,18 @@ void sim(void)
10481040 }
10491041 case 0x9D: /* (6801) */
10501042 case 0xAD: case 0xBD: /* JSR */ {
1051- if (cputype == 0x6800 && opcode == 0x9D)
1052-{ fputs( "JSR op error\n", stderr ); goto invalid16;
1053-} else {
1043+ if (cputype < 0x6801 && opcode == 0x9D)
1044+ goto invalid16;
1045+ else {
10541046 push2(pc);
10551047 jump(ea);
10561048 t->ea = ea;
10571049 }
10581050 break;
10591051 } case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
1060- if (cputype == 0x6800)
1061-{ fputs( "ADDD op error\n", stderr ); goto invalid16;
1062-} else {
1052+ if (cputype < 0x6801)
1053+ goto invalid16;
1054+ else {
10631055 setACCD( accd );
10641056 w = mread2(ea);
10651057 t->ea = ea; t->data = w;
@@ -1072,9 +1064,9 @@ void sim(void)
10721064 }
10731065 break;
10741066 } case 0xCC: case 0xDC: case 0xEC: case 0xFC: /* LDD N,Z,V=0 (6801) */ {
1075- if (cputype == 0x6800)
1076-{ fputs( "LDD op error\n", stderr ); goto invalid16;
1077-} else {
1067+ if (cputype < 0x6801)
1068+ goto invalid16;
1069+ else {
10781070 accd = mread2(ea);
10791071 t->ea = ea; t->data = accd;
10801072 z_flag = Z_16( accd );
@@ -1084,9 +1076,9 @@ void sim(void)
10841076 }
10851077 break;
10861078 } case 0xDD: case 0xED: case 0xFD: /* STD N,Z,V=0 (6801) */ {
1087- if (cputype == 0x6800)
1088-{ fputs( "STD op error\n", stderr ); goto invalid16;
1089-} else {
1079+ if (cputype < 0x6801)
1080+ goto invalid16;
1081+ else {
10901082 setACCD( accd );
10911083 n_flag = N_16( accd );
10921084 z_flag = Z_16( accd );
@@ -1111,8 +1103,6 @@ void sim(void)
11111103 break;
11121104 } default: /* ??? */ {
11131105 invalid16:
1114-fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
1115-
11161106 goto invalid;
11171107 break;
11181108 }
@@ -1255,7 +1245,7 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
12551245 case 0x01: /* NOP */ { /* Do nothing */
12561246 break;
12571247 } case 0x04: /* LSRD (6801) */ {
1258- if (cputype == 0x6800)
1248+ if (cputype < 0x6801)
12591249 goto invalidinh;
12601250 else {
12611251 setACCD( accd );
@@ -1269,7 +1259,7 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
12691259 }
12701260 break;
12711261 } case 0x05: /* LSLD (6801) */ {
1272- if (cputype == 0x6800)
1262+ if (cputype < 0x6801)
12731263 goto invalidinh;
12741264 else {
12751265 setACCD( accd );
@@ -1369,7 +1359,7 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
13691359 jump(t->ea = (pc + offset));
13701360 break;
13711361 } case 0x21: /* BRN (6801) */ {
1372- if (cputype == 0x6800)
1362+ if (cputype < 0x6801)
13731363 goto invalidinh;
13741364 else {
13751365 offset = fetch();
@@ -1485,7 +1475,7 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
14851475 push(accb);
14861476 break;
14871477 } case 0x38: /* PULX (6801) */ {
1488- if (cputype == 0x6800)
1478+ if (cputype < 0x6801)
14891479 goto invalidinh;
14901480 else {
14911481 ix = pull2();
@@ -1499,7 +1489,7 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
14991489 jump(pull2());
15001490 break;
15011491 } case 0x3A: /* ABX (6801) */ {
1502- if (cputype == 0x6800)
1492+ if (cputype < 0x6801)
15031493 goto invalidinh;
15041494 else {
15051495 ix = ix + accb;
@@ -1513,14 +1503,14 @@ fprintf( stderr, "invalid16 from opcode: %x => %x\n", t->insn[0], opcode );
15131503 jump(pull2());
15141504 break;
15151505 } case 0x3C: /* PSHX (6801) */ {
1516- if (cputype == 0x6800)
1506+ if (cputype < 0x6801)
15171507 goto invalidinh;
15181508 else {
15191509 push2(ix);
15201510 }
15211511 break;
15221512 } case 0x3D: /* MUL C=accb bit 7 (6801) */ {
1523- if (cputype == 0x6800)
1513+ if (cputype < 0x6801)
15241514 goto invalidinh;
15251515 else {
15261516 unsigned product = acca * accb;
--- a/unasm.c
+++ b/unasm.c
@@ -22,6 +22,7 @@
2222 #include <stdlib.h>
2323 #include <string.h>
2424
25+#include "exorsim.h" /* JMR20201121 */
2526 #include "utils.h"
2627 #include "unasm6800.h"
2728
@@ -50,6 +51,8 @@ int main(int argc, char *argv[])
5051 ++x;
5152 char *p = argv[x];
5253 parse_hex(&p, &addr);
54+ } else if (!strcmp(argv[x], "--6801")) {
55+ cputype = 0x6801;
5356 } else {
5457 err:
5558 printf("M6800 unassembler\n");
@@ -58,6 +61,7 @@ int main(int argc, char *argv[])
5861 printf("\n");
5962 printf(" --facts file Annotate with known facts\n");
6063 printf(" --addr hhhh Starting address of dumpfile\n");
64+ printf(" --6801 Handle additional 6801 instructions\n");
6165 exit(-1);
6266 }
6367 } else {
--- a/unasm6800.c
+++ b/unasm6800.c
@@ -267,11 +267,9 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
267267 sprintf(buf + strlen(buf), "%2.2X ", opcode = mem[pc++]);
268268
269269 if (opcode & 0x80) {
270-#ifdef SIM6801
271- if ( ((opcode & 0x0F) < 0x0C) && ((opcode & 0x0F) != 0x03) ) {
272-#else
273- if ((opcode & 0x0F) < 0x0C) {
274-#endif /* def SIM6801 */
270+ unsigned opc_det = opcode & 0x0f;
271+ if ( (cputype < 0x6801 && opc_det < 0x0C)
272+ || (opc_det < 0x0c && opc_det != 0x03) ) {
275273 /* Get operand A */
276274 if (opcode & 0x40) {
277275 sprintf(operand, "B");
@@ -321,19 +319,12 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
321319 } case 0x02: /* SBC N,Z,V,C (no H?) */ {
322320 insn = "SBC";
323321 break;
324- }
325-#ifdef SIM6801
326- case 0x03: /* ACCMD should never get here at run time. */ {
327- insn = "";
328- break;
329- }
330-#else
331- case 0x03: /* ??? */ {
322+ } case 0x03: /* ACCMD should never get here at run time when CPU is 6801? */ {
323+ if (cputype == 0x6801)
324+ fprintf( stderr, "Internal error on SUBD (6801)\n" );
332325 insn = "???";
333326 break;
334- }
335-#endif /* ndef SIM6801 */
336- case 0x04: /* AND N,Z,V=0 */ {
327+ } case 0x04: /* AND N,Z,V=0 */ {
337328 insn = "AND";
338329 break;
339330 } case 0x05: /* BIT N,Z,V=0*/ {
@@ -389,13 +380,12 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
389380 }
390381 }
391382 switch (opcode) {
392-#ifdef SIM6801
393383 case 0x83: case 0x93: case 0xA3: case 0xB3: /* SUBD N,Z,V,C (6801) */ {
394- insn = "SUBD";
384+ /* Should never come here when cputype == 0x6800. */
385+ /* But if it does, we want to do something defined. */
386+ insn = (cputype < 0x6801) ? "???SUBD" : "SUBD";
395387 break;
396- }
397-#endif /* def SIM6801 */
398- case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX N,Z,V */ {
388+ } case 0x8C: case 0x9C: case 0xAC: case 0xBC: /* CPX N,Z,V */ {
399389 insn = "CPX";
400390 break;
401391 } case 0x8D: /* BSR REL */ {
@@ -410,35 +400,36 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
410400 } case 0x8F: case 0x9F: case 0xAF: case 0xBF: /* STS N,Z,V */ {
411401 insn = "STS";
412402 break;
413- }
414-#ifdef SIM6801
415- case 0x9D: /* (6801) */
416-#endif /* def SIM6801 */
417- case 0xAD: case 0xBD: /* JSR */ {
403+ } case 0x9D: case 0xAD: case 0xBD: /* JSR */ {
404+ if (cputype < 0x6801 && opcode == 0x9D)
405+ goto invalid16;
418406 branch_target = (mem[pc - 2] << 8) + mem[pc - 1];
419407 is_jsr = 1;
420408 insn = "JSR";
421409 break;
422- }
423-#ifdef SIM6801
424- case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
410+ } case 0xC3: case 0xD3: case 0xE3: case 0xF3: /* ADDD N,Z,V,C (6801) */ {
411+ if (cputype < 0x6801)
412+ goto invalid16;
425413 insn = "ADDD";
426414 break;
427415 } case 0xCC: case 0xDC: case 0xEC: case 0xFC: /* LDD N,Z,V=0 (6801) */ {
416+ if (cputype < 0x6801)
417+ goto invalid16;
428418 insn = "LDD";
429419 break;
430420 } case 0xCD: case 0xDD: case 0xED: case 0xFD: /* STD N,Z,V=0 (6801) */ {
421+ if (cputype < 0x6801)
422+ goto invalid16;
431423 insn = "STD";
432424 break;
433- }
434-#endif /* def SIM6801 */
435- case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
425+ } case 0xCE: case 0xDE: case 0xEE: case 0xFE: /* LDX N,Z,V */ {
436426 insn = "LDX";
437427 break;
438428 } case 0xCF: case 0xDF: case 0xEF: case 0xFF: /* STX N,Z,V */ {
439429 insn = "STX";
440430 break;
441431 } default: /* ??? */ {
432+invalid16:
442433 insn = "???";
443434 break;
444435 }
@@ -520,17 +511,17 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
520511 case 0x01: /* NOP */ { /* Do nothing */
521512 insn = "NOP";
522513 break;
523- }
524-#ifdef SIM6801
525- case 0x04: /* LSRD N=0,Z,V,C (6801) */ {
514+ } case 0x04: /* LSRD N=0,Z,V,C (6801) */ {
515+ if (cputype < 0x6801)
516+ goto invalidinh;
526517 insn = "LSRD";
527518 break;
528519 } case 0x05: /* LSLD N,Z,V,C (6801) */ {
520+ if (cputype < 0x6801)
521+ goto invalidinh;
529522 insn = "LSLD";
530523 break;
531- }
532-#endif /* def SIM6801 */
533- case 0x06: /* TAP (all flags) */ {
524+ } case 0x06: /* TAP (all flags) */ {
534525 insn = "TAP";
535526 break;
536527 } case 0x07: /* TPA */ {
@@ -585,18 +576,16 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
585576 sprintf(operand + strlen(operand), " $%4.4X", branch_target);
586577 insn = "BRA";
587578 break;
588- }
589-#ifdef SIM6801
590- case 0x21: /* BRN (6801) */ {
579+ } case 0x21: /* BRN (6801) */ {
580+ if (cputype < 0x6801)
581+ goto invalidinh;
591582 offset = mem[pc++];
592583 sprintf(buf + strlen(buf), "%2.2X ", mem[pc - 1]);
593584 branch_target = pc + offset;
594585 sprintf(operand + strlen(operand), " $%4.4X", branch_target);
595586 insn = "BRN";
596587 break;
597- }
598-#endif /* def SIM6801 */
599- case 0x22: /* BHI */ {
588+ } case 0x22: /* BHI */ {
600589 offset = mem[pc++];
601590 sprintf(buf + strlen(buf), "%2.2X ", mem[pc - 1]);
602591 branch_target = pc + offset;
@@ -718,37 +707,33 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
718707 } case 0x37: /* PSHB */ {
719708 insn = "PSHB";
720709 break;
721- }
722-#ifdef SIM6801
723- case 0x38: /* PULX (6801) */ {
710+ } case 0x38: /* PULX (6801) */ {
711+ if (cputype < 0x6801)
712+ goto invalidinh;
724713 insn = "PULX";
725714 break;
726- }
727-#endif /* def SIM6801 */
728- case 0x39: /* RTS */ {
715+ } case 0x39: /* RTS */ {
729716 insn = "RTS";
730717 break;
731- }
732-#ifdef SIM6801
733- case 0x3A: /* ABX (6801) */ {
718+ } case 0x3A: /* ABX (6801) */ {
719+ if (cputype < 0x6801)
720+ goto invalidinh;
734721 insn = "ABX";
735722 break;
736- }
737-#endif /* def SIM6801 */
738- case 0x3B: /* RTI */ {
723+ } case 0x3B: /* RTI */ {
739724 insn = "RTI";
740725 break;
741- }
742-#ifdef SIM6801
743- case 0x3C: /* PSHX (6801) */ {
726+ } case 0x3C: /* PSHX (6801) */ {
727+ if (cputype < 0x6801)
728+ goto invalidinh;
744729 insn = "PSHX";
745730 break;
746731 } case 0x3D: /* MUL C=accb bit 7 (6801) */ {
732+ if (cputype < 0x6801)
733+ goto invalidinh;
747734 insn = "MUL";
748735 break;
749- }
750-#endif /* def SIM6801 */
751- case 0x3E: /* WAI */ {
736+ } case 0x3E: /* WAI */ {
752737 insn = "WAI";
753738 break;
754739 } case 0x3F: /* SWI */ {
@@ -758,6 +743,7 @@ void unasm_line(unsigned char *mem, unsigned short *at_pc, char *outbuf, int *at
758743 is_swi = mem[ea];
759744 break;
760745 } default: /* ??? */ {
746+invalidinh:
761747 insn = "???";
762748 break;
763749 }