linux-3.0.x for AP-SH4A-0A Board
Revisão | cad9b0afb809af7e7710dd8d3cf48e79eab5e276 (tree) |
---|---|
Hora | 2011-08-05 13:58:33 |
Autor | Rajashekhara, Sudhakar <sudhakar.raj@ti.c...> |
Commiter | Greg Kroah-Hartman |
ASoC: davinci: fix codec start and stop functions
commit 3012f43eaf7592d8121426918e43e3b5db013aff upstream.
According to DM365 voice codec data sheet at [1], before starting
recording or playback, ADC/DAC modules should follow a reset and
enable cycle. Writing a 1 to the ADC/DAC bit in the register resets
the module and clearing the bit to 0 will enable the module. But the
driver seems to be doing the reverse of it.
[1] http://focus.ti.com/lit/ug/sprufi9b/sprufi9b.pdf
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Acked-by: Liam Girdwood <lrg@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
@@ -62,9 +62,9 @@ static void davinci_vcif_start(struct snd_pcm_substream *substream) | ||
62 | 62 | w = readl(davinci_vc->base + DAVINCI_VC_CTRL); |
63 | 63 | |
64 | 64 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
65 | - MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1); | |
65 | + MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0); | |
66 | 66 | else |
67 | - MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1); | |
67 | + MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0); | |
68 | 68 | |
69 | 69 | writel(w, davinci_vc->base + DAVINCI_VC_CTRL); |
70 | 70 | } |
@@ -80,9 +80,9 @@ static void davinci_vcif_stop(struct snd_pcm_substream *substream) | ||
80 | 80 | /* Reset transmitter/receiver and sample rate/frame sync generators */ |
81 | 81 | w = readl(davinci_vc->base + DAVINCI_VC_CTRL); |
82 | 82 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) |
83 | - MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 0); | |
83 | + MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTDAC, 1); | |
84 | 84 | else |
85 | - MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 0); | |
85 | + MOD_REG_BIT(w, DAVINCI_VC_CTRL_RSTADC, 1); | |
86 | 86 | |
87 | 87 | writel(w, davinci_vc->base + DAVINCI_VC_CTRL); |
88 | 88 | } |