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Revisãof7cfcddd16c3f9d8385e0375d1089fa80bad1c74 (tree)
Hora2022-10-24 16:30:58
AutorJan Beulich <jbeulich@suse...>
CommiterJan Beulich

Mensagem de Log

x86: emit {evex} prefix when disassembling ambiguous AVX512VL insns

When no AVX512-specific functionality is in use, the disassembly of
AVX512VL insns is indistinguishable from their AVX counterparts (if such
exist). Emit the {evex} pseudo-prefix in such cases.

Where applicable drop stray uses of PREFIX_OPCODE from table entries.

Mudança Sumário

Diff

--- a/gas/testsuite/gas/i386/avx512f-opts-intel.d
+++ b/gas/testsuite/gas/i386/avx512f-opts-intel.d
@@ -65,8 +65,8 @@ Disassembly of section .text:
6565 [ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups zmm6\{k7\},zmm5
6666 [ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s zmm6\{k7\}\{z\},zmm5
6767 [ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups zmm6\{k7\}\{z\},zmm5
68-[ ]*[a-f0-9]+: 62 f1 fd 08 d6 ee vmovq\.s xmm6,xmm5
69-[ ]*[a-f0-9]+: 62 f1 fe 08 7e f5 vmovq xmm6,xmm5
68+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 ee \{evex\} vmovq\.s xmm6,xmm5
69+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f5 \{evex\} vmovq xmm6,xmm5
7070 [ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s zmm6,zmm5
7171 [ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd zmm6,zmm5
7272 [ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s zmm6\{k7\},zmm5
--- a/gas/testsuite/gas/i386/avx512f-opts.d
+++ b/gas/testsuite/gas/i386/avx512f-opts.d
@@ -64,8 +64,8 @@ Disassembly of section .text:
6464 [ ]*[a-f0-9]+: 62 f1 7c 4f 10 f5 vmovups %zmm5,%zmm6\{%k7\}
6565 [ ]*[a-f0-9]+: 62 f1 7c cf 11 ee vmovups.s %zmm5,%zmm6\{%k7\}\{z\}
6666 [ ]*[a-f0-9]+: 62 f1 7c cf 10 f5 vmovups %zmm5,%zmm6\{%k7\}\{z\}
67-[ ]*[a-f0-9]+: 62 f1 fd 08 d6 ee vmovq\.s %xmm5,%xmm6
68-[ ]*[a-f0-9]+: 62 f1 fe 08 7e f5 vmovq %xmm5,%xmm6
67+[ ]*[a-f0-9]+: 62 f1 fd 08 d6 ee \{evex\} vmovq\.s %xmm5,%xmm6
68+[ ]*[a-f0-9]+: 62 f1 fe 08 7e f5 \{evex\} vmovq %xmm5,%xmm6
6969 [ ]*[a-f0-9]+: 62 f1 fd 48 29 ee vmovapd.s %zmm5,%zmm6
7070 [ ]*[a-f0-9]+: 62 f1 fd 48 28 f5 vmovapd %zmm5,%zmm6
7171 [ ]*[a-f0-9]+: 62 f1 fd 4f 29 ee vmovapd.s %zmm5,%zmm6\{%k7\}
--- a/gas/testsuite/gas/i386/avx512vl_vaes-intel.d
+++ b/gas/testsuite/gas/i386/avx512vl_vaes-intel.d
@@ -33,30 +33,30 @@ Disassembly of section \.text:
3333 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4
3434 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
3535 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
36-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec xmm6,xmm5,xmm4
37-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
38-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
39-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec ymm6,ymm5,ymm4
40-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
41-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
42-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast xmm6,xmm5,xmm4
43-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
44-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
45-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast ymm6,ymm5,ymm4
46-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
47-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
48-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc xmm6,xmm5,xmm4
49-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
50-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
51-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc ymm6,ymm5,ymm4
52-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
53-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
54-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast xmm6,xmm5,xmm4
55-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
56-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
57-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4
58-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
59-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
36+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec xmm6,xmm5,xmm4
37+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
38+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
39+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec ymm6,ymm5,ymm4
40+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
41+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
42+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast xmm6,xmm5,xmm4
43+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
44+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
45+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast ymm6,ymm5,ymm4
46+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
47+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
48+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc xmm6,xmm5,xmm4
49+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
50+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
51+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc ymm6,ymm5,ymm4
52+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
53+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
54+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast xmm6,xmm5,xmm4
55+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
56+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
57+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast ymm6,ymm5,ymm4
58+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
59+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
6060 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de f4[ ]*vaesdec xmm6,xmm5,xmm4
6161 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
6262 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b2 f0 07 00 00[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
@@ -81,28 +81,28 @@ Disassembly of section \.text:
8181 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4
8282 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
8383 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
84-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec xmm6,xmm5,xmm4
85-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
86-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
87-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec ymm6,ymm5,ymm4
88-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
89-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
90-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast xmm6,xmm5,xmm4
91-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
92-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
93-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast ymm6,ymm5,ymm4
94-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
95-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
96-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc xmm6,xmm5,xmm4
97-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
98-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
99-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc ymm6,ymm5,ymm4
100-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
101-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
102-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast xmm6,xmm5,xmm4
103-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
104-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
105-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast ymm6,ymm5,ymm4
106-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
107-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
84+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec xmm6,xmm5,xmm4
85+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
86+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
87+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec ymm6,ymm5,ymm4
88+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
89+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
90+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast xmm6,xmm5,xmm4
91+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
92+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
93+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast ymm6,ymm5,ymm4
94+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
95+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
96+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc xmm6,xmm5,xmm4
97+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
98+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
99+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc ymm6,ymm5,ymm4
100+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
101+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
102+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast xmm6,xmm5,xmm4
103+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
104+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
105+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast ymm6,ymm5,ymm4
106+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
107+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
108108 #pass
--- a/gas/testsuite/gas/i386/avx512vl_vaes.d
+++ b/gas/testsuite/gas/i386/avx512vl_vaes.d
@@ -33,30 +33,30 @@ Disassembly of section \.text:
3333 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
3434 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
3535 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
36-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6
37-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
38-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
39-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6
40-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
41-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
42-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6
43-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
44-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
45-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6
46-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
47-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
48-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6
49-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
50-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
51-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6
52-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
53-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
54-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6
55-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
56-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
57-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
58-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
59-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
36+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
37+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
38+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
39+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
40+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
41+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
42+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
43+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
44+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
45+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
46+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
47+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
48+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
49+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
50+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
51+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
52+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
53+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
54+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
55+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
56+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
57+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
58+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
59+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
6060 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6
6161 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
6262 [ ]*[a-f0-9]+:[ ]*c4 e2 51 de b2 f0 07 00 00[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
@@ -81,28 +81,28 @@ Disassembly of section \.text:
8181 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
8282 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
8383 [ ]*[a-f0-9]+:[ ]*c4 e2 55 dd b2 e0 0f 00 00[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
84-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*vaesdec %xmm4,%xmm5,%xmm6
85-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
86-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
87-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*vaesdec %ymm4,%ymm5,%ymm6
88-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
89-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
90-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*vaesdeclast %xmm4,%xmm5,%xmm6
91-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
92-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
93-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*vaesdeclast %ymm4,%ymm5,%ymm6
94-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
95-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
96-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*vaesenc %xmm4,%xmm5,%xmm6
97-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
98-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
99-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*vaesenc %ymm4,%ymm5,%ymm6
100-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
101-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
102-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*vaesenclast %xmm4,%xmm5,%xmm6
103-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
104-[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
105-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*vaesenclast %ymm4,%ymm5,%ymm6
106-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
107-[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
84+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de f4[ ]*\{evex\} vaesdec %xmm4,%xmm5,%xmm6
85+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
86+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 de 72 7f[ ]*\{evex\} vaesdec 0x7f0\(%edx\),%xmm5,%xmm6
87+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de f4[ ]*\{evex\} vaesdec %ymm4,%ymm5,%ymm6
88+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdec -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
89+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 de 72 7f[ ]*\{evex\} vaesdec 0xfe0\(%edx\),%ymm5,%ymm6
90+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df f4[ ]*\{evex\} vaesdeclast %xmm4,%xmm5,%xmm6
91+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
92+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 df 72 7f[ ]*\{evex\} vaesdeclast 0x7f0\(%edx\),%xmm5,%xmm6
93+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df f4[ ]*\{evex\} vaesdeclast %ymm4,%ymm5,%ymm6
94+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df b4 f4 c0 1d fe ff[ ]*\{evex\} vaesdeclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
95+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 df 72 7f[ ]*\{evex\} vaesdeclast 0xfe0\(%edx\),%ymm5,%ymm6
96+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc f4[ ]*\{evex\} vaesenc %xmm4,%xmm5,%xmm6
97+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
98+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dc 72 7f[ ]*\{evex\} vaesenc 0x7f0\(%edx\),%xmm5,%xmm6
99+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc f4[ ]*\{evex\} vaesenc %ymm4,%ymm5,%ymm6
100+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenc -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
101+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dc 72 7f[ ]*\{evex\} vaesenc 0xfe0\(%edx\),%ymm5,%ymm6
102+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd f4[ ]*\{evex\} vaesenclast %xmm4,%xmm5,%xmm6
103+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
104+[ ]*[a-f0-9]+:[ ]*62 f2 55 08 dd 72 7f[ ]*\{evex\} vaesenclast 0x7f0\(%edx\),%xmm5,%xmm6
105+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd f4[ ]*\{evex\} vaesenclast %ymm4,%ymm5,%ymm6
106+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd b4 f4 c0 1d fe ff[ ]*\{evex\} vaesenclast -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
107+[ ]*[a-f0-9]+:[ ]*62 f2 55 28 dd 72 7f[ ]*\{evex\} vaesenclast 0xfe0\(%edx\),%ymm5,%ymm6
108108 #pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d
@@ -15,30 +15,30 @@ Disassembly of section \.text:
1515 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 e1 ab[ ]*vpclmulqdq ymm4,ymm5,ymm1,0xab
1616 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
1717 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
18-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*vpclmulqdq xmm3,xmm2,xmm2,0xab
19-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
20-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
21-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*vpclmulqdq ymm4,ymm5,ymm1,0xab
22-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
23-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
24-[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*vpclmulhqhqdq xmm4,xmm3,xmm2
25-[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*vpclmulhqlqdq xmm5,xmm4,xmm3
26-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*vpclmullqhqdq xmm6,xmm5,xmm4
27-[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*vpclmullqlqdq xmm7,xmm6,xmm5
28-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*vpclmulhqhqdq ymm3,ymm2,ymm1
29-[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*vpclmulhqlqdq ymm4,ymm3,ymm2
30-[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*vpclmullqhqdq ymm5,ymm4,ymm3
31-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*vpclmullqlqdq ymm6,ymm5,ymm4
18+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*\{evex\} vpclmulqdq xmm3,xmm2,xmm2,0xab
19+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm3,xmm2,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
20+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq xmm3,xmm2,XMMWORD PTR \[edx\+0x7f0\],0x7b
21+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*\{evex\} vpclmulqdq ymm4,ymm5,ymm1,0xab
22+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm4,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
23+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*\{evex\} vpclmulqdq ymm4,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
24+[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*\{evex\} vpclmulhqhqdq xmm4,xmm3,xmm2
25+[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*\{evex\} vpclmulhqlqdq xmm5,xmm4,xmm3
26+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*\{evex\} vpclmullqhqdq xmm6,xmm5,xmm4
27+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*\{evex\} vpclmullqlqdq xmm7,xmm6,xmm5
28+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*\{evex\} vpclmulhqhqdq ymm3,ymm2,ymm1
29+[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*\{evex\} vpclmulhqlqdq ymm4,ymm3,ymm2
30+[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*\{evex\} vpclmullqhqdq ymm5,ymm4,ymm3
31+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*\{evex\} vpclmullqlqdq ymm6,ymm5,ymm4
3232 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 db ab[ ]*vpclmulqdq xmm3,xmm5,xmm3,0xab
3333 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
3434 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9a f0 07 00 00 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
3535 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 d2 ab[ ]*vpclmulqdq ymm2,ymm2,ymm2,0xab
3636 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
3737 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
38-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*vpclmulqdq xmm3,xmm5,xmm3,0xab
39-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
40-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
41-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*vpclmulqdq ymm2,ymm2,ymm2,0xab
42-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
43-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
38+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*\{evex\} vpclmulqdq xmm3,xmm5,xmm3,0xab
39+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm3,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
40+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq xmm3,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
41+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*\{evex\} vpclmulqdq ymm2,ymm2,ymm2,0xab
42+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm2,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
43+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm2,YMMWORD PTR \[edx\+0xfe0\],0x7b
4444 #pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1-intel.d
@@ -15,22 +15,22 @@ Disassembly of section \.text:
1515 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq ymm3,ymm5,ymm2,0xab
1616 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
1717 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
18-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*vpclmulqdq xmm1,xmm1,xmm4,0xab
19-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
20-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
21-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*vpclmulqdq ymm3,ymm5,ymm2,0xab
22-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
23-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
18+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*\{evex\} vpclmulqdq xmm1,xmm1,xmm4,0xab
19+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
20+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*\{evex\} vpclmulqdq xmm1,xmm1,XMMWORD PTR \[edx\+0x7f0\],0x7b
21+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*\{evex\} vpclmulqdq ymm3,ymm5,ymm2,0xab
22+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
23+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq ymm3,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
2424 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq xmm6,xmm4,xmm1,0xab
2525 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
2626 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
2727 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq ymm2,ymm4,ymm4,0xab
2828 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
2929 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
30-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*vpclmulqdq xmm6,xmm4,xmm1,0xab
31-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
32-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
33-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*vpclmulqdq ymm2,ymm4,ymm4,0xab
34-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
35-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
30+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*\{evex\} vpclmulqdq xmm6,xmm4,xmm1,0xab
31+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
32+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*\{evex\} vpclmulqdq xmm6,xmm4,XMMWORD PTR \[edx\+0x7f0\],0x7b
33+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*\{evex\} vpclmulqdq ymm2,ymm4,ymm4,0xab
34+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
35+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq ymm2,ymm4,YMMWORD PTR \[edx\+0xfe0\],0x7b
3636 #pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq-wig1.d
@@ -15,22 +15,22 @@ Disassembly of section \.text:
1515 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 da ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
1616 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
1717 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 9a e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
18-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
19-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
20-[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
21-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
22-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
23-[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
18+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 cc ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm4,%xmm1,%xmm1
19+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 8c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm1,%xmm1
20+[ ]*[a-f0-9]+:[ ]*62 f3 f5 08 44 4a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm1,%xmm1
21+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm5,%ymm3
22+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm3
23+[ ]*[a-f0-9]+:[ ]*62 f3 d5 28 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm3
2424 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 f1 ab[ ]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
2525 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
2626 [ ]*[a-f0-9]+:[ ]*c4 e3 59 44 b2 f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
2727 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 d4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
2828 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
2929 [ ]*[a-f0-9]+:[ ]*c4 e3 5d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
30-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
31-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
32-[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
33-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
34-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
35-[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
30+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 f1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm1,%xmm4,%xmm6
31+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 b4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm4,%xmm6
32+[ ]*[a-f0-9]+:[ ]*62 f3 dd 08 44 72 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm4,%xmm6
33+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 d4 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm4,%ymm4,%ymm2
34+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm4,%ymm2
35+[ ]*[a-f0-9]+:[ ]*62 f3 dd 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm4,%ymm2
3636 #pass
--- a/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
+++ b/gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d
@@ -15,30 +15,30 @@ Disassembly of section \.text:
1515 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
1616 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
1717 [ ]*[a-f0-9]+:[ ]*c4 e3 55 44 a2 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
18-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
19-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
20-[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
21-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
22-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
23-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
24-[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*vpclmulhqhqdq %xmm2,%xmm3,%xmm4
25-[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*vpclmulhqlqdq %xmm3,%xmm4,%xmm5
26-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*vpclmullqhqdq %xmm4,%xmm5,%xmm6
27-[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*vpclmullqlqdq %xmm5,%xmm6,%xmm7
28-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*vpclmulhqhqdq %ymm1,%ymm2,%ymm3
29-[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*vpclmulhqlqdq %ymm2,%ymm3,%ymm4
30-[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*vpclmullqhqdq %ymm3,%ymm4,%ymm5
31-[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*vpclmullqlqdq %ymm4,%ymm5,%ymm6
18+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 da ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm2,%xmm2,%xmm3
19+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm2,%xmm3
20+[ ]*[a-f0-9]+:[ ]*62 f3 6d 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm2,%xmm3
21+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 e1 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm1,%ymm5,%ymm4
22+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 a4 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm4
23+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 62 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm5,%ymm4
24+[ ]*[a-f0-9]+:[ ]*62 f3 65 08 44 e2 11[ ]*\{evex\} vpclmulhqhqdq %xmm2,%xmm3,%xmm4
25+[ ]*[a-f0-9]+:[ ]*62 f3 5d 08 44 eb 01[ ]*\{evex\} vpclmulhqlqdq %xmm3,%xmm4,%xmm5
26+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 f4 10[ ]*\{evex\} vpclmullqhqdq %xmm4,%xmm5,%xmm6
27+[ ]*[a-f0-9]+:[ ]*62 f3 4d 08 44 fd 00[ ]*\{evex\} vpclmullqlqdq %xmm5,%xmm6,%xmm7
28+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d9 11[ ]*\{evex\} vpclmulhqhqdq %ymm1,%ymm2,%ymm3
29+[ ]*[a-f0-9]+:[ ]*62 f3 65 28 44 e2 01[ ]*\{evex\} vpclmulhqlqdq %ymm2,%ymm3,%ymm4
30+[ ]*[a-f0-9]+:[ ]*62 f3 5d 28 44 eb 10[ ]*\{evex\} vpclmullqhqdq %ymm3,%ymm4,%ymm5
31+[ ]*[a-f0-9]+:[ ]*62 f3 55 28 44 f4 00[ ]*\{evex\} vpclmullqlqdq %ymm4,%ymm5,%ymm6
3232 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
3333 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
3434 [ ]*[a-f0-9]+:[ ]*c4 e3 51 44 9a f0 07 00 00 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
3535 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
3636 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
3737 [ ]*[a-f0-9]+:[ ]*c4 e3 6d 44 92 e0 0f 00 00 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
38-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
39-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
40-[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
41-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
42-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
43-[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
38+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 db ab[ ]*\{evex\} vpclmulqdq \$0xab,%xmm3,%xmm5,%xmm3
39+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 9c f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm3
40+[ ]*[a-f0-9]+:[ ]*62 f3 55 08 44 5a 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0x7f0\(%edx\),%xmm5,%xmm3
41+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 d2 ab[ ]*\{evex\} vpclmulqdq \$0xab,%ymm2,%ymm2,%ymm2
42+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 94 f4 c0 1d fe ff 7b[ ]*\{evex\} vpclmulqdq \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm2,%ymm2
43+[ ]*[a-f0-9]+:[ ]*62 f3 6d 28 44 52 7f 7b[ ]*\{evex\} vpclmulqdq \$0x7b,0xfe0\(%edx\),%ymm2,%ymm2
4444 #pass
--- a/gas/testsuite/gas/i386/evex-lig-2.d
+++ b/gas/testsuite/gas/i386/evex-lig-2.d
@@ -8,28 +8,28 @@
88 Disassembly of section .text:
99
1010 0+ <_start>:
11- +[a-f0-9]+: 62 f1 7d 08 7e 21 vmovd %xmm4,\(%ecx\)
12- +[a-f0-9]+: 62 f1 7d 08 7e e1 vmovd %xmm4,%ecx
13- +[a-f0-9]+: 62 f1 7d 08 6e 21 vmovd \(%ecx\),%xmm4
14- +[a-f0-9]+: 62 f1 7d 08 6e e1 vmovd %ecx,%xmm4
15- +[a-f0-9]+: 62 f1 fd 08 d6 21 vmovq %xmm4,\(%ecx\)
16- +[a-f0-9]+: 62 f1 fe 08 7e 21 vmovq \(%ecx\),%xmm4
17- +[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
18- +[a-f0-9]+: 62 f3 7d 08 17 c0 00 vextractps \$0x0,%xmm0,%eax
19- +[a-f0-9]+: 62 f3 7d 08 17 00 00 vextractps \$0x0,%xmm0,\(%eax\)
20- +[a-f0-9]+: 62 f3 7d 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
21- +[a-f0-9]+: 62 f3 7d 08 14 00 00 vpextrb \$0x0,%xmm0,\(%eax\)
22- +[a-f0-9]+: 62 f1 7d 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
23- +[a-f0-9]+: 62 f3 7d 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
24- +[a-f0-9]+: 62 f3 7d 08 15 00 00 vpextrw \$0x0,%xmm0,\(%eax\)
25- +[a-f0-9]+: 62 f3 7d 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
26- +[a-f0-9]+: 62 f3 7d 08 16 00 00 vpextrd \$0x0,%xmm0,\(%eax\)
27- +[a-f0-9]+: 62 f3 7d 08 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
28- +[a-f0-9]+: 62 f3 7d 08 21 00 00 vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
29- +[a-f0-9]+: 62 f3 7d 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
30- +[a-f0-9]+: 62 f3 7d 08 20 00 00 vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
31- +[a-f0-9]+: 62 f1 7d 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
32- +[a-f0-9]+: 62 f1 7d 08 c4 00 00 vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
33- +[a-f0-9]+: 62 f3 7d 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
34- +[a-f0-9]+: 62 f3 7d 08 22 00 00 vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
11+ +[a-f0-9]+: 62 f1 7d 08 7e 21 \{evex\} vmovd %xmm4,\(%ecx\)
12+ +[a-f0-9]+: 62 f1 7d 08 7e e1 \{evex\} vmovd %xmm4,%ecx
13+ +[a-f0-9]+: 62 f1 7d 08 6e 21 \{evex\} vmovd \(%ecx\),%xmm4
14+ +[a-f0-9]+: 62 f1 7d 08 6e e1 \{evex\} vmovd %ecx,%xmm4
15+ +[a-f0-9]+: 62 f1 fd 08 d6 21 \{evex\} vmovq %xmm4,\(%ecx\)
16+ +[a-f0-9]+: 62 f1 fe 08 7e 21 \{evex\} vmovq \(%ecx\),%xmm4
17+ +[a-f0-9]+: 62 f1 fe 08 7e f4 \{evex\} vmovq %xmm4,%xmm6
18+ +[a-f0-9]+: 62 f3 7d 08 17 c0 00 \{evex\} vextractps \$0x0,%xmm0,%eax
19+ +[a-f0-9]+: 62 f3 7d 08 17 00 00 \{evex\} vextractps \$0x0,%xmm0,\(%eax\)
20+ +[a-f0-9]+: 62 f3 7d 08 14 c0 00 \{evex\} vpextrb \$0x0,%xmm0,%eax
21+ +[a-f0-9]+: 62 f3 7d 08 14 00 00 \{evex\} vpextrb \$0x0,%xmm0,\(%eax\)
22+ +[a-f0-9]+: 62 f1 7d 08 c5 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
23+ +[a-f0-9]+: 62 f3 7d 08 15 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
24+ +[a-f0-9]+: 62 f3 7d 08 15 00 00 \{evex\} vpextrw \$0x0,%xmm0,\(%eax\)
25+ +[a-f0-9]+: 62 f3 7d 08 16 c0 00 \{evex\} vpextrd \$0x0,%xmm0,%eax
26+ +[a-f0-9]+: 62 f3 7d 08 16 00 00 \{evex\} vpextrd \$0x0,%xmm0,\(%eax\)
27+ +[a-f0-9]+: 62 f3 7d 08 21 c0 00 \{evex\} vinsertps \$0x0,%xmm0,%xmm0,%xmm0
28+ +[a-f0-9]+: 62 f3 7d 08 21 00 00 \{evex\} vinsertps \$0x0,\(%eax\),%xmm0,%xmm0
29+ +[a-f0-9]+: 62 f3 7d 08 20 c0 00 \{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
30+ +[a-f0-9]+: 62 f3 7d 08 20 00 00 \{evex\} vpinsrb \$0x0,\(%eax\),%xmm0,%xmm0
31+ +[a-f0-9]+: 62 f1 7d 08 c4 c0 00 \{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
32+ +[a-f0-9]+: 62 f1 7d 08 c4 00 00 \{evex\} vpinsrw \$0x0,\(%eax\),%xmm0,%xmm0
33+ +[a-f0-9]+: 62 f3 7d 08 22 c0 00 \{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
34+ +[a-f0-9]+: 62 f3 7d 08 22 00 00 \{evex\} vpinsrd \$0x0,\(%eax\),%xmm0,%xmm0
3535 #pass
--- a/gas/testsuite/gas/i386/evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/evex-wig1-intel.d
@@ -9,14 +9,14 @@
99 Disassembly of section .text:
1010
1111 0+ <_start>:
12-[ ]*[a-f0-9]+: 62 f1 fe 08 2a c0 vcvtsi2ss xmm0,xmm0,eax
13-[ ]*[a-f0-9]+: 62 f1 fe 08 2a 40 01 vcvtsi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
14-[ ]*[a-f0-9]+: 62 f1 ff 08 2a c0 vcvtsi2sd xmm0,xmm0,eax
15-[ ]*[a-f0-9]+: 62 f1 ff 08 2a 40 01 vcvtsi2sd xmm0,xmm0,DWORD PTR \[eax\+0x4\]
16-[ ]*[a-f0-9]+: 62 f1 fe 08 2d c0 vcvtss2si eax,xmm0
17-[ ]*[a-f0-9]+: 62 f1 ff 08 2d c0 vcvtsd2si eax,xmm0
18-[ ]*[a-f0-9]+: 62 f1 fe 08 2c c0 vcvttss2si eax,xmm0
19-[ ]*[a-f0-9]+: 62 f1 ff 08 2c c0 vcvttsd2si eax,xmm0
12+[ ]*[a-f0-9]+: 62 f1 fe 08 2a c0 \{evex\} vcvtsi2ss xmm0,xmm0,eax
13+[ ]*[a-f0-9]+: 62 f1 fe 08 2a 40 01 \{evex\} vcvtsi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
14+[ ]*[a-f0-9]+: 62 f1 ff 08 2a c0 \{evex\} vcvtsi2sd xmm0,xmm0,eax
15+[ ]*[a-f0-9]+: 62 f1 ff 08 2a 40 01 \{evex\} vcvtsi2sd xmm0,xmm0,DWORD PTR \[eax\+0x4\]
16+[ ]*[a-f0-9]+: 62 f1 fe 08 2d c0 \{evex\} vcvtss2si eax,xmm0
17+[ ]*[a-f0-9]+: 62 f1 ff 08 2d c0 \{evex\} vcvtsd2si eax,xmm0
18+[ ]*[a-f0-9]+: 62 f1 fe 08 2c c0 \{evex\} vcvttss2si eax,xmm0
19+[ ]*[a-f0-9]+: 62 f1 ff 08 2c c0 \{evex\} vcvttsd2si eax,xmm0
2020 [ ]*[a-f0-9]+: 62 f1 fe 08 7b c0 vcvtusi2ss xmm0,xmm0,eax
2121 [ ]*[a-f0-9]+: 62 f1 fe 08 7b 40 01 vcvtusi2ss xmm0,xmm0,DWORD PTR \[eax\+0x4\]
2222 [ ]*[a-f0-9]+: 62 f1 ff 08 7b c0 vcvtusi2sd xmm0,xmm0,eax
@@ -25,26 +25,26 @@ Disassembly of section .text:
2525 [ ]*[a-f0-9]+: 62 f1 ff 08 79 c0 vcvtsd2usi eax,xmm0
2626 [ ]*[a-f0-9]+: 62 f1 fe 08 78 c0 vcvttss2usi eax,xmm0
2727 [ ]*[a-f0-9]+: 62 f1 ff 08 78 c0 vcvttsd2usi eax,xmm0
28-[ ]*[a-f0-9]+: 62 f3 fd 08 17 c0 00 vextractps eax,xmm0,0x0
29-[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 vextractps DWORD PTR \[eax\+0x4\],xmm0,0x0
30-[ ]*[a-f0-9]+: 62 f1 fd 08 6e c0 vmovd xmm0,eax
31-[ ]*[a-f0-9]+: 62 f1 fd 08 6e 40 01 vmovd xmm0,DWORD PTR \[eax\+0x4\]
32-[ ]*[a-f0-9]+: 62 f1 fd 08 7e c0 vmovd eax,xmm0
33-[ ]*[a-f0-9]+: 62 f1 fd 08 7e 40 01 vmovd DWORD PTR \[eax\+0x4\],xmm0
28+[ ]*[a-f0-9]+: 62 f3 fd 08 17 c0 00 \{evex\} vextractps eax,xmm0,0x0
29+[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 \{evex\} vextractps DWORD PTR \[eax\+0x4\],xmm0,0x0
30+[ ]*[a-f0-9]+: 62 f1 fd 08 6e c0 \{evex\} vmovd xmm0,eax
31+[ ]*[a-f0-9]+: 62 f1 fd 08 6e 40 01 \{evex\} vmovd xmm0,DWORD PTR \[eax\+0x4\]
32+[ ]*[a-f0-9]+: 62 f1 fd 08 7e c0 \{evex\} vmovd eax,xmm0
33+[ ]*[a-f0-9]+: 62 f1 fd 08 7e 40 01 \{evex\} vmovd DWORD PTR \[eax\+0x4\],xmm0
3434 [ ]*[a-f0-9]+: 62 f2 fd 08 7c c0 vpbroadcastd xmm0,eax
35-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb eax,xmm0,0x0
36-[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 vpextrb BYTE PTR \[eax\+0x1\],xmm0,0x0
37-[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrd eax,xmm0,0x0
38-[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 vpextrd DWORD PTR \[eax\+0x4\],xmm0,0x0
39-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw eax,xmm0,0x0
40-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw eax,xmm0,0x0
41-[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 vpextrw WORD PTR \[eax\+0x2\],xmm0,0x0
42-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,eax,0x0
43-[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 vpinsrb xmm0,xmm0,BYTE PTR \[eax\+0x1\],0x0
44-[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrd xmm0,xmm0,eax,0x0
45-[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
46-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
47-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
35+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 \{evex\} vpextrb eax,xmm0,0x0
36+[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 \{evex\} vpextrb BYTE PTR \[eax\+0x1\],xmm0,0x0
37+[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 \{evex\} vpextrd eax,xmm0,0x0
38+[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 \{evex\} vpextrd DWORD PTR \[eax\+0x4\],xmm0,0x0
39+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 \{evex\} vpextrw eax,xmm0,0x0
40+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 \{evex\} vpextrw eax,xmm0,0x0
41+[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 \{evex\} vpextrw WORD PTR \[eax\+0x2\],xmm0,0x0
42+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 \{evex\} vpinsrb xmm0,xmm0,eax,0x0
43+[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 \{evex\} vpinsrb xmm0,xmm0,BYTE PTR \[eax\+0x1\],0x0
44+[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 \{evex\} vpinsrd xmm0,xmm0,eax,0x0
45+[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 \{evex\} vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
46+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 \{evex\} vpinsrw xmm0,xmm0,eax,0x0
47+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 \{evex\} vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
4848 [ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss xmm0\{k7\},xmm0,xmm0
4949 [ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss xmm0\{k7\},DWORD PTR \[eax\]
5050 [ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss DWORD PTR \[eax\]\{k7\},xmm0
--- a/gas/testsuite/gas/i386/evex-wig1.d
+++ b/gas/testsuite/gas/i386/evex-wig1.d
@@ -9,14 +9,14 @@
99 Disassembly of section .text:
1010
1111 0+ <_start>:
12-[ ]*[a-f0-9]+: 62 f1 fe 08 2a c0 vcvtsi2ss %eax,%xmm0,%xmm0
13-[ ]*[a-f0-9]+: 62 f1 fe 08 2a 40 01 vcvtsi2ss 0x4\(%eax\),%xmm0,%xmm0
14-[ ]*[a-f0-9]+: 62 f1 ff 08 2a c0 vcvtsi2sd %eax,%xmm0,%xmm0
15-[ ]*[a-f0-9]+: 62 f1 ff 08 2a 40 01 vcvtsi2sd 0x4\(%eax\),%xmm0,%xmm0
16-[ ]*[a-f0-9]+: 62 f1 fe 08 2d c0 vcvtss2si %xmm0,%eax
17-[ ]*[a-f0-9]+: 62 f1 ff 08 2d c0 vcvtsd2si %xmm0,%eax
18-[ ]*[a-f0-9]+: 62 f1 fe 08 2c c0 vcvttss2si %xmm0,%eax
19-[ ]*[a-f0-9]+: 62 f1 ff 08 2c c0 vcvttsd2si %xmm0,%eax
12+[ ]*[a-f0-9]+: 62 f1 fe 08 2a c0 \{evex\} vcvtsi2ss %eax,%xmm0,%xmm0
13+[ ]*[a-f0-9]+: 62 f1 fe 08 2a 40 01 \{evex\} vcvtsi2ss 0x4\(%eax\),%xmm0,%xmm0
14+[ ]*[a-f0-9]+: 62 f1 ff 08 2a c0 \{evex\} vcvtsi2sd %eax,%xmm0,%xmm0
15+[ ]*[a-f0-9]+: 62 f1 ff 08 2a 40 01 \{evex\} vcvtsi2sd 0x4\(%eax\),%xmm0,%xmm0
16+[ ]*[a-f0-9]+: 62 f1 fe 08 2d c0 \{evex\} vcvtss2si %xmm0,%eax
17+[ ]*[a-f0-9]+: 62 f1 ff 08 2d c0 \{evex\} vcvtsd2si %xmm0,%eax
18+[ ]*[a-f0-9]+: 62 f1 fe 08 2c c0 \{evex\} vcvttss2si %xmm0,%eax
19+[ ]*[a-f0-9]+: 62 f1 ff 08 2c c0 \{evex\} vcvttsd2si %xmm0,%eax
2020 [ ]*[a-f0-9]+: 62 f1 fe 08 7b c0 vcvtusi2ss %eax,%xmm0,%xmm0
2121 [ ]*[a-f0-9]+: 62 f1 fe 08 7b 40 01 vcvtusi2ss 0x4\(%eax\),%xmm0,%xmm0
2222 [ ]*[a-f0-9]+: 62 f1 ff 08 7b c0 vcvtusi2sd %eax,%xmm0,%xmm0
@@ -25,26 +25,26 @@ Disassembly of section .text:
2525 [ ]*[a-f0-9]+: 62 f1 ff 08 79 c0 vcvtsd2usi %xmm0,%eax
2626 [ ]*[a-f0-9]+: 62 f1 fe 08 78 c0 vcvttss2usi %xmm0,%eax
2727 [ ]*[a-f0-9]+: 62 f1 ff 08 78 c0 vcvttsd2usi %xmm0,%eax
28-[ ]*[a-f0-9]+: 62 f3 fd 08 17 c0 00 vextractps \$0x0,%xmm0,%eax
29-[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 vextractps \$0x0,%xmm0,0x4\(%eax\)
30-[ ]*[a-f0-9]+: 62 f1 fd 08 6e c0 vmovd %eax,%xmm0
31-[ ]*[a-f0-9]+: 62 f1 fd 08 6e 40 01 vmovd 0x4\(%eax\),%xmm0
32-[ ]*[a-f0-9]+: 62 f1 fd 08 7e c0 vmovd %xmm0,%eax
33-[ ]*[a-f0-9]+: 62 f1 fd 08 7e 40 01 vmovd %xmm0,0x4\(%eax\)
28+[ ]*[a-f0-9]+: 62 f3 fd 08 17 c0 00 \{evex\} vextractps \$0x0,%xmm0,%eax
29+[ ]*[a-f0-9]+: 62 f3 fd 08 17 40 01 00 \{evex\} vextractps \$0x0,%xmm0,0x4\(%eax\)
30+[ ]*[a-f0-9]+: 62 f1 fd 08 6e c0 \{evex\} vmovd %eax,%xmm0
31+[ ]*[a-f0-9]+: 62 f1 fd 08 6e 40 01 \{evex\} vmovd 0x4\(%eax\),%xmm0
32+[ ]*[a-f0-9]+: 62 f1 fd 08 7e c0 \{evex\} vmovd %xmm0,%eax
33+[ ]*[a-f0-9]+: 62 f1 fd 08 7e 40 01 \{evex\} vmovd %xmm0,0x4\(%eax\)
3434 [ ]*[a-f0-9]+: 62 f2 fd 08 7c c0 vpbroadcastd %eax,%xmm0
35-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
36-[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 vpextrb \$0x0,%xmm0,0x1\(%eax\)
37-[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
38-[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 vpextrd \$0x0,%xmm0,0x4\(%eax\)
39-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
40-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
41-[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 vpextrw \$0x0,%xmm0,0x2\(%eax\)
42-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
43-[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 vpinsrb \$0x0,0x1\(%eax\),%xmm0,%xmm0
44-[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
45-[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
46-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
47-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
35+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 \{evex\} vpextrb \$0x0,%xmm0,%eax
36+[ ]*[a-f0-9]+: 62 f3 fd 08 14 40 01 00 \{evex\} vpextrb \$0x0,%xmm0,0x1\(%eax\)
37+[ ]*[a-f0-9]+: 62 f3 fd 08 16 c0 00 \{evex\} vpextrd \$0x0,%xmm0,%eax
38+[ ]*[a-f0-9]+: 62 f3 fd 08 16 40 01 00 \{evex\} vpextrd \$0x0,%xmm0,0x4\(%eax\)
39+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
40+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
41+[ ]*[a-f0-9]+: 62 f3 fd 08 15 40 01 00 \{evex\} vpextrw \$0x0,%xmm0,0x2\(%eax\)
42+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 \{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
43+[ ]*[a-f0-9]+: 62 f3 fd 08 20 40 01 00 \{evex\} vpinsrb \$0x0,0x1\(%eax\),%xmm0,%xmm0
44+[ ]*[a-f0-9]+: 62 f3 fd 08 22 c0 00 \{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
45+[ ]*[a-f0-9]+: 62 f3 fd 08 22 40 01 00 \{evex\} vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
46+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 \{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
47+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 40 01 00 \{evex\} vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
4848 [ ]*[a-f0-9]+: 62 f1 7e 0f 10 c0 vmovss %xmm0,%xmm0,%xmm0\{%k7\}
4949 [ ]*[a-f0-9]+: 62 f1 7e 0f 10 00 vmovss \(%eax\),%xmm0\{%k7\}
5050 [ ]*[a-f0-9]+: 62 f1 7e 0f 11 00 vmovss %xmm0,\(%eax\)\{%k7\}
--- a/gas/testsuite/gas/i386/evex.d
+++ b/gas/testsuite/gas/i386/evex.d
@@ -16,6 +16,6 @@ Disassembly of section .text:
1616 +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
1717 +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
1818 +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\{rd-bad\},%xmm5,%xmm6
19- +[a-f0-9]+: 62 e1 7e 08 2d c0 vcvtss2si %xmm0,%eax
19+ +[a-f0-9]+: 62 e1 7e 08 2d c0 \{evex\} vcvtss2si %xmm0,%eax
2020 +[a-f0-9]+: 62 e1 7c 08 c2 c0 00 vcmpeqps %xmm0,%xmm0,%k0
2121 #pass
--- a/gas/testsuite/gas/i386/noreg16-data32.d
+++ b/gas/testsuite/gas/i386/noreg16-data32.d
@@ -141,9 +141,9 @@ Disassembly of section .text:
141141 *[a-f0-9]+: 66 f7 07 89 00 00 00 testl \$0x89,\(%bx\)
142142 *[a-f0-9]+: 66 f7 07 34 12 00 00 testl \$0x1234,\(%bx\)
143143 *[a-f0-9]+: c5 fb 2a 07 vcvtsi2sd \(%bx\),%xmm0,%xmm0
144- *[a-f0-9]+: 62 f1 7f 08 2a 07 vcvtsi2sd \(%bx\),%xmm0,%xmm0
144+ *[a-f0-9]+: 62 f1 7f 08 2a 07 \{evex\} vcvtsi2sd \(%bx\),%xmm0,%xmm0
145145 *[a-f0-9]+: c5 fa 2a 07 vcvtsi2ss \(%bx\),%xmm0,%xmm0
146- *[a-f0-9]+: 62 f1 7e 08 2a 07 vcvtsi2ss \(%bx\),%xmm0,%xmm0
146+ *[a-f0-9]+: 62 f1 7e 08 2a 07 \{evex\} vcvtsi2ss \(%bx\),%xmm0,%xmm0
147147 *[a-f0-9]+: 62 f1 7f 08 7b 07 vcvtusi2sd \(%bx\),%xmm0,%xmm0
148148 *[a-f0-9]+: 62 f1 7e 08 7b 07 vcvtusi2ss \(%bx\),%xmm0,%xmm0
149149 *[a-f0-9]+: 66 83 37 01 xorl \$0x1,\(%bx\)
--- a/gas/testsuite/gas/i386/noreg16.d
+++ b/gas/testsuite/gas/i386/noreg16.d
@@ -140,9 +140,9 @@ Disassembly of section .text:
140140 *[a-f0-9]+: f7 07 89 00 testw \$0x89,\(%bx\)
141141 *[a-f0-9]+: f7 07 34 12 testw \$0x1234,\(%bx\)
142142 *[a-f0-9]+: c5 fb 2a 07 vcvtsi2sd \(%bx\),%xmm0,%xmm0
143- *[a-f0-9]+: 62 f1 7f 08 2a 07 vcvtsi2sd \(%bx\),%xmm0,%xmm0
143+ *[a-f0-9]+: 62 f1 7f 08 2a 07 \{evex\} vcvtsi2sd \(%bx\),%xmm0,%xmm0
144144 *[a-f0-9]+: c5 fa 2a 07 vcvtsi2ss \(%bx\),%xmm0,%xmm0
145- *[a-f0-9]+: 62 f1 7e 08 2a 07 vcvtsi2ss \(%bx\),%xmm0,%xmm0
145+ *[a-f0-9]+: 62 f1 7e 08 2a 07 \{evex\} vcvtsi2ss \(%bx\),%xmm0,%xmm0
146146 *[a-f0-9]+: 62 f1 7f 08 7b 07 vcvtusi2sd \(%bx\),%xmm0,%xmm0
147147 *[a-f0-9]+: 62 f1 7e 08 7b 07 vcvtusi2ss \(%bx\),%xmm0,%xmm0
148148 *[a-f0-9]+: 83 37 01 xorw \$0x1,\(%bx\)
--- a/gas/testsuite/gas/i386/noreg32-data16.d
+++ b/gas/testsuite/gas/i386/noreg32-data16.d
@@ -151,9 +151,9 @@ Disassembly of section .text:
151151 *[a-f0-9]+: 66 f7 00 34 12 testw \$0x1234,\(%eax\)
152152 *[a-f0-9]+: 66 f7 00 78 56 testw \$0x5678,\(%eax\)
153153 *[a-f0-9]+: c5 fb 2a 00 vcvtsi2sd \(%eax\),%xmm0,%xmm0
154- *[a-f0-9]+: 62 f1 7f 08 2a 00 vcvtsi2sd \(%eax\),%xmm0,%xmm0
154+ *[a-f0-9]+: 62 f1 7f 08 2a 00 \{evex\} vcvtsi2sd \(%eax\),%xmm0,%xmm0
155155 *[a-f0-9]+: c5 fa 2a 00 vcvtsi2ss \(%eax\),%xmm0,%xmm0
156- *[a-f0-9]+: 62 f1 7e 08 2a 00 vcvtsi2ss \(%eax\),%xmm0,%xmm0
156+ *[a-f0-9]+: 62 f1 7e 08 2a 00 \{evex\} vcvtsi2ss \(%eax\),%xmm0,%xmm0
157157 *[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sd \(%eax\),%xmm0,%xmm0
158158 *[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ss \(%eax\),%xmm0,%xmm0
159159 *[a-f0-9]+: 66 83 30 01 xorw \$0x1,\(%eax\)
--- a/gas/testsuite/gas/i386/noreg32.d
+++ b/gas/testsuite/gas/i386/noreg32.d
@@ -149,9 +149,9 @@ Disassembly of section .text:
149149 *[a-f0-9]+: f7 00 34 12 00 00 testl \$0x1234,\(%eax\)
150150 *[a-f0-9]+: f7 00 78 56 34 12 testl \$0x12345678,\(%eax\)
151151 *[a-f0-9]+: c5 fb 2a 00 vcvtsi2sd \(%eax\),%xmm0,%xmm0
152- *[a-f0-9]+: 62 f1 7f 08 2a 00 vcvtsi2sd \(%eax\),%xmm0,%xmm0
152+ *[a-f0-9]+: 62 f1 7f 08 2a 00 \{evex\} vcvtsi2sd \(%eax\),%xmm0,%xmm0
153153 *[a-f0-9]+: c5 fa 2a 00 vcvtsi2ss \(%eax\),%xmm0,%xmm0
154- *[a-f0-9]+: 62 f1 7e 08 2a 00 vcvtsi2ss \(%eax\),%xmm0,%xmm0
154+ *[a-f0-9]+: 62 f1 7e 08 2a 00 \{evex\} vcvtsi2ss \(%eax\),%xmm0,%xmm0
155155 *[a-f0-9]+: 62 f1 7f 08 7b 00 vcvtusi2sd \(%eax\),%xmm0,%xmm0
156156 *[a-f0-9]+: 62 f1 7e 08 7b 00 vcvtusi2ss \(%eax\),%xmm0,%xmm0
157157 *[a-f0-9]+: 83 30 01 xorl \$0x1,\(%eax\)
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -601,7 +601,7 @@ Disassembly of section .text:
601601 +[a-f0-9]+: 82 eb 01 sub bl,0x1
602602 +[a-f0-9]+: 82 f3 01 xor bl,0x1
603603 +[a-f0-9]+: 82 fb 01 cmp bl,0x1
604- +[a-f0-9]+: 62 f3 7d 08 15 e8 ab vpextrw eax,xmm5,0xab
604+ +[a-f0-9]+: 62 f3 7d 08 15 e8 ab \{evex\} vpextrw eax,xmm5,0xab
605605 +[a-f0-9]+: f6 c9 01 test cl,(0x)?0*1
606606 +[a-f0-9]+: 66 f7 c9 02 00 test cx,(0x)?0*2
607607 +[a-f0-9]+: f7 c9 04 00 00 00 test ecx,(0x)?0*4
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -601,5 +601,5 @@ Disassembly of section .text:
601601 +[a-f0-9]+: 82 eb 01 subb \$0x1,%bl
602602 +[a-f0-9]+: 82 f3 01 xorb \$0x1,%bl
603603 +[a-f0-9]+: 82 fb 01 cmpb \$0x1,%bl
604- +[a-f0-9]+: 62 f3 7d 08 15 e8 ab vpextrw \$0xab,%xmm5,%eax
604+ +[a-f0-9]+: 62 f3 7d 08 15 e8 ab \{evex\} vpextrw \$0xab,%xmm5,%eax
605605 #pass
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -600,7 +600,7 @@ Disassembly of section .text:
600600 +[a-f0-9]+: 82 eb 01 sub \$0x1,%bl
601601 +[a-f0-9]+: 82 f3 01 xor \$0x1,%bl
602602 +[a-f0-9]+: 82 fb 01 cmp \$0x1,%bl
603- +[a-f0-9]+: 62 f3 7d 08 15 e8 ab vpextrw \$0xab,%xmm5,%eax
603+ +[a-f0-9]+: 62 f3 7d 08 15 e8 ab \{evex\} vpextrw \$0xab,%xmm5,%eax
604604 +[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
605605 +[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
606606 +[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
--- a/gas/testsuite/gas/i386/optimize-4.d
+++ b/gas/testsuite/gas/i386/optimize-4.d
@@ -147,6 +147,6 @@ Disassembly of section .text:
147147 +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
148148 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
149149 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
150- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
151- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
150+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
151+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
152152 #pass
--- a/gas/testsuite/gas/i386/optimize-5.d
+++ b/gas/testsuite/gas/i386/optimize-5.d
@@ -147,8 +147,8 @@ Disassembly of section .text:
147147 +[a-f0-9]+: 62 .* vporq 0x80\(%eax\),%ymm2,%ymm3
148148 +[a-f0-9]+: 62 .* vpxord 0x80\(%eax\),%ymm2,%ymm3
149149 +[a-f0-9]+: 62 .* vpxorq 0x80\(%eax\),%ymm2,%ymm3
150- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
151- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
150+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
151+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
152152 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
153153 +[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
154154 +[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/prefix.d
+++ b/gas/testsuite/gas/i386/prefix.d
@@ -89,7 +89,7 @@ Disassembly of section .text:
8989 [ ]*[a-f0-9]+: 66 c5 f8 28 c0 data16 vmovaps %xmm0,%xmm0
9090 [ ]*[a-f0-9]+: f3 c4 e1 78 28 c0 repz vmovaps %xmm0,%xmm0
9191 [ ]*[a-f0-9]+: f2 c5 f8 28 c0 repnz vmovaps %xmm0,%xmm0
92-[ ]*[a-f0-9]+: f0 62 f1 7c 08 28 c0 lock vmovaps %xmm0,%xmm0
92+[ ]*[a-f0-9]+: f0 62 f1 7c 08 28 c0 lock \{evex\} vmovaps %xmm0,%xmm0
9393 [ ]*[a-f0-9]+: c5 fb e6 40 20 vcvtpd2dqx 0x20\(%eax\),%xmm0
9494 [ ]*[a-f0-9]+: 62 f1 ff 18 e6 40 04 vcvtpd2dq 0x20\(%eax\)\{1to2\},%xmm0
9595 [ ]*[a-f0-9]+: c5 fb e6 40 20 vcvtpd2dqx 0x20\(%eax\),%xmm0
--- a/gas/testsuite/gas/i386/pseudos.d
+++ b/gas/testsuite/gas/i386/pseudos.d
@@ -18,15 +18,15 @@ Disassembly of section .text:
1818 +[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%eax\),%xmm2
1919 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
2020 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
21- +[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%eax\),%xmm2
21+ +[a-f0-9]+: 62 f1 7c 08 28 10 \{evex\} vmovaps \(%eax\),%xmm2
2222 +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
23- +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
24- +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
23+ +[a-f0-9]+: 62 f1 7c 08 28 50 00 \{evex\} vmovaps 0x0\(%eax\),%xmm2
24+ +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 \{evex\} vmovaps 0x0\(%eax\),%xmm2
2525 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
2626 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
27- +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
28- +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
29- +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
27+ +[a-f0-9]+: 62 f1 7c 08 28 50 08 \{evex\} vmovaps 0x80\(%eax\),%xmm2
28+ +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 \{evex\} vmovaps 0x80\(%bx\),%xmm2
29+ +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 \{evex\} vmovaps 0x80\(%eax\),%xmm2
3030 +[a-f0-9]+: 89 c8 mov %ecx,%eax
3131 +[a-f0-9]+: 8b c1 mov %ecx,%eax
3232 +[a-f0-9]+: 89 c8 mov %ecx,%eax
@@ -267,18 +267,18 @@ Disassembly of section .text:
267267 +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
268268 +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
269269 +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
270- +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
271- +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
272- +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
270+ +[a-f0-9]+: 62 f1 fe 08 7e f8 \{evex\} vmovq %xmm0,%xmm7
271+ +[a-f0-9]+: 62 f1 fe 08 7e f8 \{evex\} vmovq %xmm0,%xmm7
272+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 \{evex\} vmovq %xmm0,%xmm7
273273 +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
274274 +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
275275 +[a-f0-9]+: 66 0f 3a 15 c7 00 pextrw \$0x0,%xmm0,%edi
276276 +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
277277 +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
278278 +[a-f0-9]+: c4 e3 79 15 c7 00 vpextrw \$0x0,%xmm0,%edi
279- +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
280- +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
281- +[a-f0-9]+: 62 f3 7d 08 15 c7 00 vpextrw \$0x0,%xmm0,%edi
279+ +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
280+ +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
281+ +[a-f0-9]+: 62 f3 7d 08 15 c7 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
282282 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
283283 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
284284 +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
@@ -318,15 +318,15 @@ Disassembly of section .text:
318318 +[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%eax\),%xmm2
319319 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
320320 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%eax\),%xmm2
321- +[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%eax\),%xmm2
321+ +[a-f0-9]+: 62 f1 7c 08 28 10 \{evex\} vmovaps \(%eax\),%xmm2
322322 +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
323- +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%eax\),%xmm2
324- +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%eax\),%xmm2
323+ +[a-f0-9]+: 62 f1 7c 08 28 50 00 \{evex\} vmovaps 0x0\(%eax\),%xmm2
324+ +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 \{evex\} vmovaps 0x0\(%eax\),%xmm2
325325 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
326326 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
327- +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%eax\),%xmm2
328- +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 vmovaps 0x80\(%bx\),%xmm2
329- +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%eax\),%xmm2
327+ +[a-f0-9]+: 62 f1 7c 08 28 50 08 \{evex\} vmovaps 0x80\(%eax\),%xmm2
328+ +[a-f0-9]+: 67 62 f1 7c 08 28 97 80 00 \{evex\} vmovaps 0x80\(%bx\),%xmm2
329+ +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 \{evex\} vmovaps 0x80\(%eax\),%xmm2
330330 +[a-f0-9]+: 89 c8 mov %ecx,%eax
331331 +[a-f0-9]+: 8b c1 mov %ecx,%eax
332332 +[a-f0-9]+: 89 c8 mov %ecx,%eax
--- a/gas/testsuite/gas/i386/x86-64-evex-lig-2.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-lig-2.d
@@ -8,34 +8,34 @@
88 Disassembly of section .text:
99
1010 0+ <_start>:
11- +[a-f0-9]+: 62 f1 7d 08 7e 21 vmovd %xmm4,\(%rcx\)
12- +[a-f0-9]+: 62 f1 7d 08 7e e1 vmovd %xmm4,%ecx
13- +[a-f0-9]+: 62 f1 7d 08 6e 21 vmovd \(%rcx\),%xmm4
14- +[a-f0-9]+: 62 f1 7d 08 6e e1 vmovd %ecx,%xmm4
15- +[a-f0-9]+: 62 f1 fd 08 7e 21 vmovq %xmm4,\(%rcx\)
16- +[a-f0-9]+: 62 f1 fd 08 7e e1 vmovq %xmm4,%rcx
17- +[a-f0-9]+: 62 f1 fd 08 6e 21 vmovq \(%rcx\),%xmm4
18- +[a-f0-9]+: 62 f1 fd 08 6e e1 vmovq %rcx,%xmm4
19- +[a-f0-9]+: 62 f1 fe 08 7e f4 vmovq %xmm4,%xmm6
20- +[a-f0-9]+: 62 f3 7d 08 17 c0 00 vextractps \$0x0,%xmm0,%eax
21- +[a-f0-9]+: 62 f3 7d 08 17 00 00 vextractps \$0x0,%xmm0,\(%rax\)
22- +[a-f0-9]+: 62 f3 7d 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
23- +[a-f0-9]+: 62 f3 7d 08 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
24- +[a-f0-9]+: 62 f1 7d 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
25- +[a-f0-9]+: 62 f3 7d 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
26- +[a-f0-9]+: 62 f3 7d 08 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
27- +[a-f0-9]+: 62 f3 7d 08 16 c0 00 vpextrd \$0x0,%xmm0,%eax
28- +[a-f0-9]+: 62 f3 7d 08 16 00 00 vpextrd \$0x0,%xmm0,\(%rax\)
29- +[a-f0-9]+: 62 f3 fd 08 16 c0 00 vpextrq \$0x0,%xmm0,%rax
30- +[a-f0-9]+: 62 f3 fd 08 16 00 00 vpextrq \$0x0,%xmm0,\(%rax\)
31- +[a-f0-9]+: 62 f3 7d 08 21 c0 00 vinsertps \$0x0,%xmm0,%xmm0,%xmm0
32- +[a-f0-9]+: 62 f3 7d 08 21 00 00 vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
33- +[a-f0-9]+: 62 f3 7d 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
34- +[a-f0-9]+: 62 f3 7d 08 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
35- +[a-f0-9]+: 62 f1 7d 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
36- +[a-f0-9]+: 62 f1 7d 08 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
37- +[a-f0-9]+: 62 f3 7d 08 22 c0 00 vpinsrd \$0x0,%eax,%xmm0,%xmm0
38- +[a-f0-9]+: 62 f3 7d 08 22 00 00 vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
39- +[a-f0-9]+: 62 f3 fd 08 22 c0 00 vpinsrq \$0x0,%rax,%xmm0,%xmm0
40- +[a-f0-9]+: 62 f3 fd 08 22 00 00 vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
11+ +[a-f0-9]+: 62 f1 7d 08 7e 21 \{evex\} vmovd %xmm4,\(%rcx\)
12+ +[a-f0-9]+: 62 f1 7d 08 7e e1 \{evex\} vmovd %xmm4,%ecx
13+ +[a-f0-9]+: 62 f1 7d 08 6e 21 \{evex\} vmovd \(%rcx\),%xmm4
14+ +[a-f0-9]+: 62 f1 7d 08 6e e1 \{evex\} vmovd %ecx,%xmm4
15+ +[a-f0-9]+: 62 f1 fd 08 7e 21 \{evex\} vmovq %xmm4,\(%rcx\)
16+ +[a-f0-9]+: 62 f1 fd 08 7e e1 \{evex\} vmovq %xmm4,%rcx
17+ +[a-f0-9]+: 62 f1 fd 08 6e 21 \{evex\} vmovq \(%rcx\),%xmm4
18+ +[a-f0-9]+: 62 f1 fd 08 6e e1 \{evex\} vmovq %rcx,%xmm4
19+ +[a-f0-9]+: 62 f1 fe 08 7e f4 \{evex\} vmovq %xmm4,%xmm6
20+ +[a-f0-9]+: 62 f3 7d 08 17 c0 00 \{evex\} vextractps \$0x0,%xmm0,%eax
21+ +[a-f0-9]+: 62 f3 7d 08 17 00 00 \{evex\} vextractps \$0x0,%xmm0,\(%rax\)
22+ +[a-f0-9]+: 62 f3 7d 08 14 c0 00 \{evex\} vpextrb \$0x0,%xmm0,%eax
23+ +[a-f0-9]+: 62 f3 7d 08 14 00 00 \{evex\} vpextrb \$0x0,%xmm0,\(%rax\)
24+ +[a-f0-9]+: 62 f1 7d 08 c5 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
25+ +[a-f0-9]+: 62 f3 7d 08 15 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
26+ +[a-f0-9]+: 62 f3 7d 08 15 00 00 \{evex\} vpextrw \$0x0,%xmm0,\(%rax\)
27+ +[a-f0-9]+: 62 f3 7d 08 16 c0 00 \{evex\} vpextrd \$0x0,%xmm0,%eax
28+ +[a-f0-9]+: 62 f3 7d 08 16 00 00 \{evex\} vpextrd \$0x0,%xmm0,\(%rax\)
29+ +[a-f0-9]+: 62 f3 fd 08 16 c0 00 \{evex\} vpextrq \$0x0,%xmm0,%rax
30+ +[a-f0-9]+: 62 f3 fd 08 16 00 00 \{evex\} vpextrq \$0x0,%xmm0,\(%rax\)
31+ +[a-f0-9]+: 62 f3 7d 08 21 c0 00 \{evex\} vinsertps \$0x0,%xmm0,%xmm0,%xmm0
32+ +[a-f0-9]+: 62 f3 7d 08 21 00 00 \{evex\} vinsertps \$0x0,\(%rax\),%xmm0,%xmm0
33+ +[a-f0-9]+: 62 f3 7d 08 20 c0 00 \{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
34+ +[a-f0-9]+: 62 f3 7d 08 20 00 00 \{evex\} vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
35+ +[a-f0-9]+: 62 f1 7d 08 c4 c0 00 \{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
36+ +[a-f0-9]+: 62 f1 7d 08 c4 00 00 \{evex\} vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
37+ +[a-f0-9]+: 62 f3 7d 08 22 c0 00 \{evex\} vpinsrd \$0x0,%eax,%xmm0,%xmm0
38+ +[a-f0-9]+: 62 f3 7d 08 22 00 00 \{evex\} vpinsrd \$0x0,\(%rax\),%xmm0,%xmm0
39+ +[a-f0-9]+: 62 f3 fd 08 22 c0 00 \{evex\} vpinsrq \$0x0,%rax,%xmm0,%xmm0
40+ +[a-f0-9]+: 62 f3 fd 08 22 00 00 \{evex\} vpinsrq \$0x0,\(%rax\),%xmm0,%xmm0
4141 #pass
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1-intel.d
@@ -18,15 +18,15 @@ Disassembly of section .text:
1818 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps DWORD PTR \[rdx\+0x200\],xmm29,0x7b
1919 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps DWORD PTR \[rdx-0x200\],xmm29,0x7b
2020 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps DWORD PTR \[rdx-0x204\],xmm29,0x7b
21-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb eax,xmm0,0x0
22-[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb BYTE PTR \[rax\],xmm0,0x0
23-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw eax,xmm0,0x0
24-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw eax,xmm0,0x0
25-[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw WORD PTR \[rax\],xmm0,0x0
26-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb xmm0,xmm0,eax,0x0
27-[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
28-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw xmm0,xmm0,eax,0x0
29-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
21+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 \{evex\} vpextrb eax,xmm0,0x0
22+[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 \{evex\} vpextrb BYTE PTR \[rax\],xmm0,0x0
23+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 \{evex\} vpextrw eax,xmm0,0x0
24+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 \{evex\} vpextrw eax,xmm0,0x0
25+[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 \{evex\} vpextrw WORD PTR \[rax\],xmm0,0x0
26+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 \{evex\} vpinsrb xmm0,xmm0,eax,0x0
27+[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 \{evex\} vpinsrb xmm0,xmm0,BYTE PTR \[rax\],0x0
28+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 \{evex\} vpinsrw xmm0,xmm0,eax,0x0
29+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 \{evex\} vpinsrw xmm0,xmm0,WORD PTR \[rax\],0x0
3030 [ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd zmm30\{k7\},xmm29
3131 [ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd zmm30\{k7\}\{z\},xmm29
3232 [ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd zmm30\{k7\},XMMWORD PTR \[rcx\]
--- a/gas/testsuite/gas/i386/x86-64-evex-wig1.d
+++ b/gas/testsuite/gas/i386/x86-64-evex-wig1.d
@@ -18,15 +18,15 @@ Disassembly of section .text:
1818 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa 00 02 00 00 7b vextractps \$0x7b,%xmm29,0x200\(%rdx\)
1919 [ ]*[a-f0-9]+: 62 63 fd 08 17 6a 80 7b vextractps \$0x7b,%xmm29,-0x200\(%rdx\)
2020 [ ]*[a-f0-9]+: 62 63 fd 08 17 aa fc fd ff ff 7b vextractps \$0x7b,%xmm29,-0x204\(%rdx\)
21-[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 vpextrb \$0x0,%xmm0,%eax
22-[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 vpextrb \$0x0,%xmm0,\(%rax\)
23-[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 vpextrw \$0x0,%xmm0,%eax
24-[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 vpextrw \$0x0,%xmm0,%eax
25-[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 vpextrw \$0x0,%xmm0,\(%rax\)
26-[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 vpinsrb \$0x0,%eax,%xmm0,%xmm0
27-[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
28-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 vpinsrw \$0x0,%eax,%xmm0,%xmm0
29-[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
21+[ ]*[a-f0-9]+: 62 f3 fd 08 14 c0 00 \{evex\} vpextrb \$0x0,%xmm0,%eax
22+[ ]*[a-f0-9]+: 62 f3 fd 08 14 00 00 \{evex\} vpextrb \$0x0,%xmm0,\(%rax\)
23+[ ]*[a-f0-9]+: 62 f1 fd 08 c5 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
24+[ ]*[a-f0-9]+: 62 f3 fd 08 15 c0 00 \{evex\} vpextrw \$0x0,%xmm0,%eax
25+[ ]*[a-f0-9]+: 62 f3 fd 08 15 00 00 \{evex\} vpextrw \$0x0,%xmm0,\(%rax\)
26+[ ]*[a-f0-9]+: 62 f3 fd 08 20 c0 00 \{evex\} vpinsrb \$0x0,%eax,%xmm0,%xmm0
27+[ ]*[a-f0-9]+: 62 f3 fd 08 20 00 00 \{evex\} vpinsrb \$0x0,\(%rax\),%xmm0,%xmm0
28+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 c0 00 \{evex\} vpinsrw \$0x0,%eax,%xmm0,%xmm0
29+[ ]*[a-f0-9]+: 62 f1 fd 08 c4 00 00 \{evex\} vpinsrw \$0x0,\(%rax\),%xmm0,%xmm0
3030 [ ]*[a-f0-9]+: 62 02 fd 4f 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}
3131 [ ]*[a-f0-9]+: 62 02 fd cf 21 f5 vpmovsxbd %xmm29,%zmm30\{%k7\}\{z\}
3232 [ ]*[a-f0-9]+: 62 62 fd 4f 21 31 vpmovsxbd \(%rcx\),%zmm30\{%k7\}
--- a/gas/testsuite/gas/i386/x86-64-movd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-movd-intel.d
@@ -16,8 +16,8 @@ Disassembly of section .text:
1616 +[a-f0-9]+: c4 e1 f9 6e c8 vmovq xmm1,rax
1717 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd DWORD PTR \[rax\+0x80\],xmm1
1818 +[a-f0-9]+: c4 e1 f9 7e c8 vmovq rax,xmm1
19- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd xmm1,DWORD PTR \[rax\+0x80\]
20- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1
19+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
20+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
2121 +[a-f0-9]+: 66 0f 6e 88 80 00 00 00 movd xmm1,DWORD PTR \[rax\+0x80\]
2222 +[a-f0-9]+: 66 0f 6e 88 80 00 00 00 movd xmm1,DWORD PTR \[rax\+0x80\]
2323 +[a-f0-9]+: 66 0f 6e c8 movd xmm1,eax
@@ -34,12 +34,12 @@ Disassembly of section .text:
3434 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd DWORD PTR \[rax\+0x80\],xmm1
3535 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd DWORD PTR \[rax\+0x80\],xmm1
3636 +[a-f0-9]+: c5 f9 7e c8 vmovd eax,xmm1
37- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd xmm1,DWORD PTR \[rax\+0x80\]
38- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd xmm1,DWORD PTR \[rax\+0x80\]
39- +[a-f0-9]+: 62 f1 7d 08 6e c8 vmovd xmm1,eax
40- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1
41- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd DWORD PTR \[rax\+0x80\],xmm1
42- +[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd eax,xmm1
37+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
38+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd xmm1,DWORD PTR \[rax\+0x80\]
39+ +[a-f0-9]+: 62 f1 7d 08 6e c8 \{evex\} vmovd xmm1,eax
40+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
41+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd DWORD PTR \[rax\+0x80\],xmm1
42+ +[a-f0-9]+: 62 f1 7d 08 7e c8 \{evex\} vmovd eax,xmm1
4343 +[a-f0-9]+: c4 e1 f9 6e c8 vmovq xmm1,rax
4444 +[a-f0-9]+: c4 e1 f9 7e c8 vmovq rax,xmm1
4545 #pass
--- a/gas/testsuite/gas/i386/x86-64-movd.d
+++ b/gas/testsuite/gas/i386/x86-64-movd.d
@@ -15,8 +15,8 @@ Disassembly of section .text:
1515 +[a-f0-9]+: c4 e1 f9 6e c8 vmovq %rax,%xmm1
1616 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd %xmm1,0x80\(%rax\)
1717 +[a-f0-9]+: c4 e1 f9 7e c8 vmovq %xmm1,%rax
18- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd 0x80\(%rax\),%xmm1
19- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\)
18+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd 0x80\(%rax\),%xmm1
19+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd %xmm1,0x80\(%rax\)
2020 +[a-f0-9]+: 66 0f 6e 88 80 00 00 00 movd 0x80\(%rax\),%xmm1
2121 +[a-f0-9]+: 66 0f 6e 88 80 00 00 00 movd 0x80\(%rax\),%xmm1
2222 +[a-f0-9]+: 66 0f 6e c8 movd %eax,%xmm1
@@ -33,12 +33,12 @@ Disassembly of section .text:
3333 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd %xmm1,0x80\(%rax\)
3434 +[a-f0-9]+: c5 f9 7e 88 80 00 00 00 vmovd %xmm1,0x80\(%rax\)
3535 +[a-f0-9]+: c5 f9 7e c8 vmovd %xmm1,%eax
36- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd 0x80\(%rax\),%xmm1
37- +[a-f0-9]+: 62 f1 7d 08 6e 48 20 vmovd 0x80\(%rax\),%xmm1
38- +[a-f0-9]+: 62 f1 7d 08 6e c8 vmovd %eax,%xmm1
39- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\)
40- +[a-f0-9]+: 62 f1 7d 08 7e 48 20 vmovd %xmm1,0x80\(%rax\)
41- +[a-f0-9]+: 62 f1 7d 08 7e c8 vmovd %xmm1,%eax
36+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd 0x80\(%rax\),%xmm1
37+ +[a-f0-9]+: 62 f1 7d 08 6e 48 20 \{evex\} vmovd 0x80\(%rax\),%xmm1
38+ +[a-f0-9]+: 62 f1 7d 08 6e c8 \{evex\} vmovd %eax,%xmm1
39+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd %xmm1,0x80\(%rax\)
40+ +[a-f0-9]+: 62 f1 7d 08 7e 48 20 \{evex\} vmovd %xmm1,0x80\(%rax\)
41+ +[a-f0-9]+: 62 f1 7d 08 7e c8 \{evex\} vmovd %xmm1,%eax
4242 +[a-f0-9]+: c4 e1 f9 6e c8 vmovq %rax,%xmm1
4343 +[a-f0-9]+: c4 e1 f9 7e c8 vmovq %xmm1,%rax
4444 #pass
--- a/gas/testsuite/gas/i386/x86-64-optimize-5.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-5.d
@@ -203,8 +203,8 @@ Disassembly of section .text:
203203 +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
204204 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
205205 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
206- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
207- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
206+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
207+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
208208 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
209209 +[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
210210 +[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-optimize-6.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-6.d
@@ -203,8 +203,8 @@ Disassembly of section .text:
203203 +[a-f0-9]+: 62 .* vporq 0x80\(%rax\),%ymm2,%ymm3
204204 +[a-f0-9]+: 62 .* vpxord 0x80\(%rax\),%ymm2,%ymm3
205205 +[a-f0-9]+: 62 .* vpxorq 0x80\(%rax\),%ymm2,%ymm3
206- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
207- +[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
206+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
207+ +[a-f0-9]+: 62 f1 f5 08 55 e9 \{evex\} vandnpd %xmm1,%xmm1,%xmm5
208208 +[a-f0-9]+: 62 f1 7d 28 6f d1 vmovdqa32 %ymm1,%ymm2
209209 +[a-f0-9]+: 62 f1 fd 28 6f d1 vmovdqa64 %ymm1,%ymm2
210210 +[a-f0-9]+: 62 f1 7f 08 6f d1 vmovdqu8 %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-pseudos.d
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.d
@@ -18,14 +18,14 @@ Disassembly of section .text:
1818 +[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%rax\),%xmm2
1919 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%rax\),%xmm2
2020 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%rax\),%xmm2
21- +[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%rax\),%xmm2
21+ +[a-f0-9]+: 62 f1 7c 08 28 10 \{evex\} vmovaps \(%rax\),%xmm2
2222 +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
23- +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
24- +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
23+ +[a-f0-9]+: 62 f1 7c 08 28 50 00 \{evex\} vmovaps 0x0\(%rax\),%xmm2
24+ +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 \{evex\} vmovaps 0x0\(%rax\),%xmm2
2525 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
2626 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
27- +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%rax\),%xmm2
28- +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
27+ +[a-f0-9]+: 62 f1 7c 08 28 50 08 \{evex\} vmovaps 0x80\(%rax\),%xmm2
28+ +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 \{evex\} vmovaps 0x80\(%rax\),%xmm2
2929 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
3030 +[a-f0-9]+: 48 8b c1 mov %rcx,%rax
3131 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
@@ -278,18 +278,18 @@ Disassembly of section .text:
278278 +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
279279 +[a-f0-9]+: c5 fa 7e f8 vmovq %xmm0,%xmm7
280280 +[a-f0-9]+: c5 f9 d6 c7 vmovq %xmm0,%xmm7
281- +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
282- +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7
283- +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7
281+ +[a-f0-9]+: 62 f1 fe 08 7e f8 \{evex\} vmovq %xmm0,%xmm7
282+ +[a-f0-9]+: 62 f1 fe 08 7e f8 \{evex\} vmovq %xmm0,%xmm7
283+ +[a-f0-9]+: 62 f1 fd 08 d6 c7 \{evex\} vmovq %xmm0,%xmm7
284284 +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
285285 +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi
286286 +[a-f0-9]+: 66 0f 3a 15 c7 00 pextrw \$0x0,%xmm0,%edi
287287 +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
288288 +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
289289 +[a-f0-9]+: c4 e3 79 15 c7 00 vpextrw \$0x0,%xmm0,%edi
290- +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
291- +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi
292- +[a-f0-9]+: 62 f3 7d 08 15 c7 00 vpextrw \$0x0,%xmm0,%edi
290+ +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
291+ +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
292+ +[a-f0-9]+: 62 f3 7d 08 15 c7 00 \{evex\} vpextrw \$0x0,%xmm0,%edi
293293 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
294294 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0
295295 +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0
@@ -341,14 +341,14 @@ Disassembly of section .text:
341341 +[a-f0-9]+: c4 e1 78 28 10 vmovaps \(%rax\),%xmm2
342342 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%rax\),%xmm2
343343 +[a-f0-9]+: c5 f8 28 10 vmovaps \(%rax\),%xmm2
344- +[a-f0-9]+: 62 f1 7c 08 28 10 vmovaps \(%rax\),%xmm2
344+ +[a-f0-9]+: 62 f1 7c 08 28 10 \{evex\} vmovaps \(%rax\),%xmm2
345345 +[a-f0-9]+: c5 f8 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
346- +[a-f0-9]+: 62 f1 7c 08 28 50 00 vmovaps 0x0\(%rax\),%xmm2
347- +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 vmovaps 0x0\(%rax\),%xmm2
346+ +[a-f0-9]+: 62 f1 7c 08 28 50 00 \{evex\} vmovaps 0x0\(%rax\),%xmm2
347+ +[a-f0-9]+: 62 f1 7c 08 28 90 00 00 00 00 \{evex\} vmovaps 0x0\(%rax\),%xmm2
348348 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
349349 +[a-f0-9]+: c5 f8 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
350- +[a-f0-9]+: 62 f1 7c 08 28 50 08 vmovaps 0x80\(%rax\),%xmm2
351- +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 vmovaps 0x80\(%rax\),%xmm2
350+ +[a-f0-9]+: 62 f1 7c 08 28 50 08 \{evex\} vmovaps 0x80\(%rax\),%xmm2
351+ +[a-f0-9]+: 62 f1 7c 08 28 90 80 00 00 00 \{evex\} vmovaps 0x80\(%rax\),%xmm2
352352 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
353353 +[a-f0-9]+: 48 8b c1 mov %rcx,%rax
354354 +[a-f0-9]+: 48 89 c8 mov %rcx,%rax
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -2,7 +2,7 @@ static const struct dis386 evex_len_table[][3] = {
22 /* EVEX_LEN_0F3816 */
33 {
44 { Bad_Opcode },
5- { "vpermp%XW", { XM, Vex, EXx }, PREFIX_DATA },
5+ { "%XEvpermp%XW", { XM, Vex, EXx }, PREFIX_DATA },
66 { "vpermp%XW", { XM, Vex, EXx }, PREFIX_DATA },
77 },
88
@@ -30,7 +30,7 @@ static const struct dis386 evex_len_table[][3] = {
3030 /* EVEX_LEN_0F3836 */
3131 {
3232 { Bad_Opcode },
33- { "vperm%DQ", { XM, Vex, EXx }, PREFIX_DATA },
33+ { "%XEvperm%DQ", { XM, Vex, EXx }, PREFIX_DATA },
3434 { "vperm%DQ", { XM, Vex, EXx }, PREFIX_DATA },
3535 },
3636
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -1,8 +1,8 @@
11 /* PREFIX_EVEX_0F5B */
22 {
33 { VEX_W_TABLE (EVEX_W_0F5B_P_0) },
4- { "vcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
5- { "vcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
4+ { "%XEvcvttp%XS2dq", { XM, EXx, EXxEVexS }, 0 },
5+ { "%XEvcvtp%XS2dq", { XM, EXx, EXxEVexR }, 0 },
66 },
77 /* PREFIX_EVEX_0F6F */
88 {
@@ -14,9 +14,9 @@
1414 /* PREFIX_EVEX_0F70 */
1515 {
1616 { Bad_Opcode },
17- { "vpshufhw", { XM, EXx, Ib }, 0 },
17+ { "%XEvpshufhw", { XM, EXx, Ib }, 0 },
1818 { VEX_W_TABLE (EVEX_W_0F70_P_2) },
19- { "vpshuflw", { XM, EXx, Ib }, 0 },
19+ { "%XEvpshuflw", { XM, EXx, Ib }, 0 },
2020 },
2121 /* PREFIX_EVEX_0F78 */
2222 {
@@ -70,8 +70,8 @@
7070 {
7171 { Bad_Opcode },
7272 { VEX_W_TABLE (EVEX_W_0FE6_P_1) },
73- { "vcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
74- { "vcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
73+ { "%XEvcvttp%XD2dq%XY", { XMxmmq, EXx, EXxEVexS }, 0 },
74+ { "%XEvcvtp%XD2dq%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
7575 },
7676 /* PREFIX_EVEX_0F3810 */
7777 {
@@ -95,7 +95,7 @@
9595 {
9696 { Bad_Opcode },
9797 { VEX_W_TABLE (EVEX_W_0F3813_P_1) },
98- { "vcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
98+ { "%XEvcvtph2p%XS", { XM, EXxmmq, EXxEVexS }, 0 },
9999 },
100100 /* PREFIX_EVEX_0F3814 */
101101 {
@@ -113,31 +113,31 @@
113113 {
114114 { Bad_Opcode },
115115 { VEX_W_TABLE (EVEX_W_0F3820_P_1) },
116- { "vpmovsxbw", { XM, EXxmmq }, 0 },
116+ { "%XEvpmovsxbw", { XM, EXxmmq }, 0 },
117117 },
118118 /* PREFIX_EVEX_0F3821 */
119119 {
120120 { Bad_Opcode },
121121 { VEX_W_TABLE (EVEX_W_0F3821_P_1) },
122- { "vpmovsxbd", { XM, EXxmmqd }, 0 },
122+ { "%XEvpmovsxbd", { XM, EXxmmqd }, 0 },
123123 },
124124 /* PREFIX_EVEX_0F3822 */
125125 {
126126 { Bad_Opcode },
127127 { VEX_W_TABLE (EVEX_W_0F3822_P_1) },
128- { "vpmovsxbq", { XM, EXxmmdw }, 0 },
128+ { "%XEvpmovsxbq", { XM, EXxmmdw }, 0 },
129129 },
130130 /* PREFIX_EVEX_0F3823 */
131131 {
132132 { Bad_Opcode },
133133 { VEX_W_TABLE (EVEX_W_0F3823_P_1) },
134- { "vpmovsxwd", { XM, EXxmmq }, 0 },
134+ { "%XEvpmovsxwd", { XM, EXxmmq }, 0 },
135135 },
136136 /* PREFIX_EVEX_0F3824 */
137137 {
138138 { Bad_Opcode },
139139 { VEX_W_TABLE (EVEX_W_0F3824_P_1) },
140- { "vpmovsxwq", { XM, EXxmmqd }, 0 },
140+ { "%XEvpmovsxwq", { XM, EXxmmqd }, 0 },
141141 },
142142 /* PREFIX_EVEX_0F3825 */
143143 {
@@ -179,31 +179,31 @@
179179 {
180180 { Bad_Opcode },
181181 { VEX_W_TABLE (EVEX_W_0F3830_P_1) },
182- { "vpmovzxbw", { XM, EXxmmq }, 0 },
182+ { "%XEvpmovzxbw", { XM, EXxmmq }, 0 },
183183 },
184184 /* PREFIX_EVEX_0F3831 */
185185 {
186186 { Bad_Opcode },
187187 { VEX_W_TABLE (EVEX_W_0F3831_P_1) },
188- { "vpmovzxbd", { XM, EXxmmqd }, 0 },
188+ { "%XEvpmovzxbd", { XM, EXxmmqd }, 0 },
189189 },
190190 /* PREFIX_EVEX_0F3832 */
191191 {
192192 { Bad_Opcode },
193193 { VEX_W_TABLE (EVEX_W_0F3832_P_1) },
194- { "vpmovzxbq", { XM, EXxmmdw }, 0 },
194+ { "%XEvpmovzxbq", { XM, EXxmmdw }, 0 },
195195 },
196196 /* PREFIX_EVEX_0F3833 */
197197 {
198198 { Bad_Opcode },
199199 { VEX_W_TABLE (EVEX_W_0F3833_P_1) },
200- { "vpmovzxwd", { XM, EXxmmq }, 0 },
200+ { "%XEvpmovzxwd", { XM, EXxmmq }, 0 },
201201 },
202202 /* PREFIX_EVEX_0F3834 */
203203 {
204204 { Bad_Opcode },
205205 { VEX_W_TABLE (EVEX_W_0F3834_P_1) },
206- { "vpmovzxwq", { XM, EXxmmqd }, 0 },
206+ { "%XEvpmovzxwq", { XM, EXxmmqd }, 0 },
207207 },
208208 /* PREFIX_EVEX_0F3835 */
209209 {
@@ -215,19 +215,19 @@
215215 {
216216 { Bad_Opcode },
217217 { MOD_TABLE (MOD_EVEX_0F3838_P_1) },
218- { "vpminsb", { XM, Vex, EXx }, 0 },
218+ { "%XEvpminsb", { XM, Vex, EXx }, 0 },
219219 },
220220 /* PREFIX_EVEX_0F3839 */
221221 {
222222 { Bad_Opcode },
223223 { "vpmov%DQ2m", { MaskG, EXx }, 0 },
224- { "vpmins%DQ", { XM, Vex, EXx }, 0 },
224+ { "%XEvpmins%DQ", { XM, Vex, EXx }, 0 },
225225 },
226226 /* PREFIX_EVEX_0F383A */
227227 {
228228 { Bad_Opcode },
229229 { VEX_W_TABLE (EVEX_W_0F383A_P_1) },
230- { "vpminuw", { XM, Vex, EXx }, 0 },
230+ { "%XEvpminuw", { XM, Vex, EXx }, 0 },
231231 },
232232 /* PREFIX_EVEX_0F3852 */
233233 {
@@ -261,28 +261,28 @@
261261 {
262262 { Bad_Opcode },
263263 { Bad_Opcode },
264- { "vfmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
264+ { "%XEvfmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
265265 { "v4fmaddp%XS", { XM, Vex, Mxmm }, 0 },
266266 },
267267 /* PREFIX_EVEX_0F389B */
268268 {
269269 { Bad_Opcode },
270270 { Bad_Opcode },
271- { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
271+ { "%XEvfmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
272272 { "v4fmadds%XS", { XMScalar, VexScalar, Mxmm }, 0 },
273273 },
274274 /* PREFIX_EVEX_0F38AA */
275275 {
276276 { Bad_Opcode },
277277 { Bad_Opcode },
278- { "vfmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
278+ { "%XEvfmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
279279 { "v4fnmaddp%XS", { XM, Vex, Mxmm }, 0 },
280280 },
281281 /* PREFIX_EVEX_0F38AB */
282282 {
283283 { Bad_Opcode },
284284 { Bad_Opcode },
285- { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
285+ { "%XEvfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
286286 { "v4fnmadds%XS", { XMScalar, VexScalar, Mxmm }, 0 },
287287 },
288288 /* PREFIX_EVEX_0F3A08 */
--- a/opcodes/i386-dis-evex-reg.h
+++ b/opcodes/i386-dis-evex-reg.h
@@ -2,11 +2,11 @@
22 {
33 { Bad_Opcode },
44 { Bad_Opcode },
5- { "vpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
5+ { "%XEvpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
66 { Bad_Opcode },
7- { "vpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
7+ { "%XEvpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
88 { Bad_Opcode },
9- { "vpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
9+ { "%XEvpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
1010 },
1111 /* REG_EVEX_0F72 */
1212 {
@@ -14,7 +14,7 @@
1414 { "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
1515 { VEX_W_TABLE (EVEX_W_0F72_R_2) },
1616 { Bad_Opcode },
17- { "vpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
17+ { "%XEvpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
1818 { Bad_Opcode },
1919 { VEX_W_TABLE (EVEX_W_0F72_R_6) },
2020 },
@@ -23,11 +23,11 @@
2323 { Bad_Opcode },
2424 { Bad_Opcode },
2525 { VEX_W_TABLE (EVEX_W_0F73_R_2) },
26- { "vpsrldq", { Vex, EXx, Ib }, PREFIX_DATA },
26+ { "%XEvpsrldq", { Vex, EXx, Ib }, PREFIX_DATA },
2727 { Bad_Opcode },
2828 { Bad_Opcode },
2929 { VEX_W_TABLE (EVEX_W_0F73_R_6) },
30- { "vpslldq", { Vex, EXx, Ib }, PREFIX_DATA },
30+ { "%XEvpslldq", { Vex, EXx, Ib }, PREFIX_DATA },
3131 },
3232 /* REG_EVEX_0F38C6_M_0_L_2 */
3333 {
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -1,11 +1,11 @@
11 /* EVEX_W_0F5B_P_0 */
22 {
3- { "vcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
3+ { "%XEvcvtdq2ps", { XM, EXx, EXxEVexR }, 0 },
44 { "vcvtqq2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
55 },
66 /* EVEX_W_0F62 */
77 {
8- { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
8+ { "%XEvpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
99 },
1010 /* EVEX_W_0F66 */
1111 {
@@ -13,21 +13,21 @@
1313 },
1414 /* EVEX_W_0F6A */
1515 {
16- { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
16+ { "%XEvpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
1717 },
1818 /* EVEX_W_0F6B */
1919 {
20- { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
20+ { "%XEvpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
2121 },
2222 /* EVEX_W_0F6C */
2323 {
2424 { Bad_Opcode },
25- { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
25+ { "%XEvpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
2626 },
2727 /* EVEX_W_0F6D */
2828 {
2929 { Bad_Opcode },
30- { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
30+ { "%XEvpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
3131 },
3232 /* EVEX_W_0F6F_P_1 */
3333 {
@@ -46,25 +46,25 @@
4646 },
4747 /* EVEX_W_0F70_P_2 */
4848 {
49- { "vpshufd", { XM, EXx, Ib }, 0 },
49+ { "%XEvpshufd", { XM, EXx, Ib }, 0 },
5050 },
5151 /* EVEX_W_0F72_R_2 */
5252 {
53- { "vpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
53+ { "%XEvpsrld", { Vex, EXx, Ib }, PREFIX_DATA },
5454 },
5555 /* EVEX_W_0F72_R_6 */
5656 {
57- { "vpslld", { Vex, EXx, Ib }, PREFIX_DATA },
57+ { "%XEvpslld", { Vex, EXx, Ib }, PREFIX_DATA },
5858 },
5959 /* EVEX_W_0F73_R_2 */
6060 {
6161 { Bad_Opcode },
62- { "vpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
62+ { "%XEvpsrlq", { Vex, EXx, Ib }, PREFIX_DATA },
6363 },
6464 /* EVEX_W_0F73_R_6 */
6565 {
6666 { Bad_Opcode },
67- { "vpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
67+ { "%XEvpsllq", { Vex, EXx, Ib }, PREFIX_DATA },
6868 },
6969 /* EVEX_W_0F76 */
7070 {
@@ -132,17 +132,17 @@
132132 },
133133 /* EVEX_W_0FD2 */
134134 {
135- { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
135+ { "%XEvpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
136136 },
137137 /* EVEX_W_0FD3 */
138138 {
139139 { Bad_Opcode },
140- { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
140+ { "%XEvpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
141141 },
142142 /* EVEX_W_0FD4 */
143143 {
144144 { Bad_Opcode },
145- { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
145+ { "%XEvpaddq", { XM, Vex, EXx }, PREFIX_DATA },
146146 },
147147 /* EVEX_W_0FD6 */
148148 {
@@ -151,39 +151,39 @@
151151 },
152152 /* EVEX_W_0FE6_P_1 */
153153 {
154- { "vcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
154+ { "%XEvcvtdq2pd", { XM, EXEvexHalfBcstXmmq }, 0 },
155155 { "vcvtqq2pd", { XM, EXx, EXxEVexR }, 0 },
156156 },
157157 /* EVEX_W_0FE7 */
158158 {
159- { "vmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
159+ { "%XEvmovntdq", { EXEvexXNoBcst, XM }, PREFIX_DATA },
160160 },
161161 /* EVEX_W_0FF2 */
162162 {
163- { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
163+ { "%XEvpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
164164 },
165165 /* EVEX_W_0FF3 */
166166 {
167167 { Bad_Opcode },
168- { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
168+ { "%XEvpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
169169 },
170170 /* EVEX_W_0FF4 */
171171 {
172172 { Bad_Opcode },
173- { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
173+ { "%XEvpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
174174 },
175175 /* EVEX_W_0FFA */
176176 {
177- { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
177+ { "%XEvpsubd", { XM, Vex, EXx }, PREFIX_DATA },
178178 },
179179 /* EVEX_W_0FFB */
180180 {
181181 { Bad_Opcode },
182- { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
182+ { "%XEvpsubq", { XM, Vex, EXx }, PREFIX_DATA },
183183 },
184184 /* EVEX_W_0FFE */
185185 {
186- { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
186+ { "%XEvpaddd", { XM, Vex, EXx }, PREFIX_DATA },
187187 },
188188 /* EVEX_W_0F3810_P_1 */
189189 {
@@ -227,7 +227,7 @@
227227 /* EVEX_W_0F3819_L_n */
228228 {
229229 { "vbroadcastf32x2", { XM, EXq }, PREFIX_DATA },
230- { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
230+ { "%XEvbroadcastsd", { XM, EXq }, PREFIX_DATA },
231231 },
232232 /* EVEX_W_0F381A_M_0_L_n */
233233 {
@@ -241,7 +241,7 @@
241241 },
242242 /* EVEX_W_0F381E */
243243 {
244- { "vpabsd", { XM, EXx }, PREFIX_DATA },
244+ { "%XEvpabsd", { XM, EXx }, PREFIX_DATA },
245245 },
246246 /* EVEX_W_0F381F */
247247 {
@@ -274,12 +274,12 @@
274274 },
275275 /* EVEX_W_0F3825_P_2 */
276276 {
277- { "vpmovsxdq", { XM, EXxmmq }, 0 },
277+ { "%XEvpmovsxdq", { XM, EXxmmq }, 0 },
278278 },
279279 /* EVEX_W_0F3828_P_2 */
280280 {
281281 { Bad_Opcode },
282- { "vpmuldq", { XM, Vex, EXx }, 0 },
282+ { "%XEvpmuldq", { XM, Vex, EXx }, 0 },
283283 },
284284 /* EVEX_W_0F3829_P_2 */
285285 {
@@ -293,11 +293,11 @@
293293 },
294294 /* EVEX_W_0F382A_P_2 */
295295 {
296- { "vmovntdqa", { XM, EXEvexXNoBcst }, 0 },
296+ { "%XEvmovntdqa", { XM, EXEvexXNoBcst }, 0 },
297297 },
298298 /* EVEX_W_0F382B */
299299 {
300- { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
300+ { "%XEvpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
301301 },
302302 /* EVEX_W_0F3830_P_1 */
303303 {
@@ -325,7 +325,7 @@
325325 },
326326 /* EVEX_W_0F3835_P_2 */
327327 {
328- { "vpmovzxdq", { XM, EXxmmq }, 0 },
328+ { "%XEvpmovzxdq", { XM, EXxmmq }, 0 },
329329 },
330330 /* EVEX_W_0F3837 */
331331 {
@@ -339,7 +339,7 @@
339339 /* EVEX_W_0F3859 */
340340 {
341341 { "vbroadcasti32x2", { XM, EXq }, PREFIX_DATA },
342- { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
342+ { "%XEvpbroadcastq", { XM, EXq }, PREFIX_DATA },
343343 },
344344 /* EVEX_W_0F385A_M_0_L_n */
345345 {
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -24,8 +24,8 @@ static const struct dis386 evex_table[][256] = {
2424 { PREFIX_TABLE (PREFIX_VEX_0F11) },
2525 { PREFIX_TABLE (PREFIX_VEX_0F12) },
2626 { MOD_TABLE (MOD_VEX_0F13) },
27- { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
28- { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
27+ { "%XEvunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
28+ { "%XEvunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
2929 { PREFIX_TABLE (PREFIX_VEX_0F16) },
3030 { MOD_TABLE (MOD_VEX_0F17) },
3131 /* 18 */
@@ -47,8 +47,8 @@ static const struct dis386 evex_table[][256] = {
4747 { Bad_Opcode },
4848 { Bad_Opcode },
4949 /* 28 */
50- { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
51- { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
50+ { "%XEvmovapX", { XM, EXx }, PREFIX_OPCODE },
51+ { "%XEvmovapX", { EXxS, XM }, PREFIX_OPCODE },
5252 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5353 { MOD_TABLE (MOD_VEX_0F2B) },
5454 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
@@ -96,10 +96,10 @@ static const struct dis386 evex_table[][256] = {
9696 { PREFIX_TABLE (PREFIX_VEX_0F51) },
9797 { Bad_Opcode },
9898 { Bad_Opcode },
99- { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
100- { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
101- { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
102- { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
99+ { "%XEvandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
100+ { "%XEvandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
101+ { "%XEvorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
102+ { "%XEvxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
103103 /* 58 */
104104 { PREFIX_TABLE (PREFIX_VEX_0F58) },
105105 { PREFIX_TABLE (PREFIX_VEX_0F59) },
@@ -110,17 +110,17 @@ static const struct dis386 evex_table[][256] = {
110110 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
111111 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
112112 /* 60 */
113- { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
114- { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
113+ { "%XEvpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
114+ { "%XEvpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
115115 { VEX_W_TABLE (EVEX_W_0F62) },
116- { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
116+ { "%XEvpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
117117 { "vpcmpgtb", { MaskG, Vex, EXx }, PREFIX_DATA },
118118 { "vpcmpgtw", { MaskG, Vex, EXx }, PREFIX_DATA },
119119 { VEX_W_TABLE (EVEX_W_0F66) },
120- { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
120+ { "%XEvpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
121121 /* 68 */
122- { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
123- { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
122+ { "%XEvpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
123+ { "%XEvpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
124124 { VEX_W_TABLE (EVEX_W_0F6A) },
125125 { VEX_W_TABLE (EVEX_W_0F6B) },
126126 { VEX_W_TABLE (EVEX_W_0F6C) },
@@ -224,7 +224,7 @@ static const struct dis386 evex_table[][256] = {
224224 { Bad_Opcode },
225225 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
226226 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
227- { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
227+ { "%XEvshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
228228 { Bad_Opcode },
229229 /* C8 */
230230 { Bad_Opcode },
@@ -237,67 +237,67 @@ static const struct dis386 evex_table[][256] = {
237237 { Bad_Opcode },
238238 /* D0 */
239239 { Bad_Opcode },
240- { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
240+ { "%XEvpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
241241 { VEX_W_TABLE (EVEX_W_0FD2) },
242242 { VEX_W_TABLE (EVEX_W_0FD3) },
243243 { VEX_W_TABLE (EVEX_W_0FD4) },
244- { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
244+ { "%XEvpmullw", { XM, Vex, EXx }, PREFIX_DATA },
245245 { VEX_W_TABLE (EVEX_W_0FD6) },
246246 { Bad_Opcode },
247247 /* D8 */
248- { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
249- { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
250- { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
248+ { "%XEvpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
249+ { "%XEvpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
250+ { "%XEvpminub", { XM, Vex, EXx }, PREFIX_DATA },
251251 { "vpand%DQ", { XM, Vex, EXx }, PREFIX_DATA },
252- { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
253- { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
254- { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
252+ { "%XEvpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
253+ { "%XEvpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
254+ { "%XEvpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
255255 { "vpandn%DQ", { XM, Vex, EXx }, PREFIX_DATA },
256256 /* E0 */
257- { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
258- { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
259- { "vpsra%DQ", { XM, Vex, EXxmm }, PREFIX_DATA },
260- { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
261- { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
262- { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
257+ { "%XEvpavgb", { XM, Vex, EXx }, PREFIX_DATA },
258+ { "%XEvpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
259+ { "%XEvpsra%DQ", { XM, Vex, EXxmm }, PREFIX_DATA },
260+ { "%XEvpavgw", { XM, Vex, EXx }, PREFIX_DATA },
261+ { "%XEvpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
262+ { "%XEvpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
263263 { PREFIX_TABLE (PREFIX_EVEX_0FE6) },
264264 { VEX_W_TABLE (EVEX_W_0FE7) },
265265 /* E8 */
266- { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
267- { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
268- { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
266+ { "%XEvpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
267+ { "%XEvpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
268+ { "%XEvpminsw", { XM, Vex, EXx }, PREFIX_DATA },
269269 { "vpor%DQ", { XM, Vex, EXx }, PREFIX_DATA },
270- { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
271- { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
272- { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
270+ { "%XEvpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
271+ { "%XEvpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
272+ { "%XEvpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
273273 { "vpxor%DQ", { XM, Vex, EXx }, PREFIX_DATA },
274274 /* F0 */
275275 { Bad_Opcode },
276- { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
276+ { "%XEvpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
277277 { VEX_W_TABLE (EVEX_W_0FF2) },
278278 { VEX_W_TABLE (EVEX_W_0FF3) },
279279 { VEX_W_TABLE (EVEX_W_0FF4) },
280- { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
281- { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
280+ { "%XEvpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
281+ { "%XEvpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
282282 { Bad_Opcode },
283283 /* F8 */
284- { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
285- { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
284+ { "%XEvpsubb", { XM, Vex, EXx }, PREFIX_DATA },
285+ { "%XEvpsubw", { XM, Vex, EXx }, PREFIX_DATA },
286286 { VEX_W_TABLE (EVEX_W_0FFA) },
287287 { VEX_W_TABLE (EVEX_W_0FFB) },
288- { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
289- { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
288+ { "%XEvpaddb", { XM, Vex, EXx }, PREFIX_DATA },
289+ { "%XEvpaddw", { XM, Vex, EXx }, PREFIX_DATA },
290290 { VEX_W_TABLE (EVEX_W_0FFE) },
291291 { Bad_Opcode },
292292 },
293293 /* EVEX_0F38 */
294294 {
295295 /* 00 */
296- { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
296+ { "%XEvpshufb", { XM, Vex, EXx }, PREFIX_DATA },
297297 { Bad_Opcode },
298298 { Bad_Opcode },
299299 { Bad_Opcode },
300- { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
300+ { "%XEvpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
301301 { Bad_Opcode },
302302 { Bad_Opcode },
303303 { Bad_Opcode },
@@ -305,9 +305,9 @@ static const struct dis386 evex_table[][256] = {
305305 { Bad_Opcode },
306306 { Bad_Opcode },
307307 { Bad_Opcode },
308- { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
308+ { "%XEvpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
309309 { VEX_W_TABLE (VEX_W_0F380C) },
310- { "vpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
310+ { "%XEvpermilp%XD", { XM, Vex, EXx }, PREFIX_DATA },
311311 { Bad_Opcode },
312312 { Bad_Opcode },
313313 /* 10 */
@@ -324,8 +324,8 @@ static const struct dis386 evex_table[][256] = {
324324 { EVEX_LEN_TABLE (EVEX_LEN_0F3819) },
325325 { MOD_TABLE (MOD_EVEX_0F381A) },
326326 { MOD_TABLE (MOD_EVEX_0F381B) },
327- { "vpabsb", { XM, EXx }, PREFIX_DATA },
328- { "vpabsw", { XM, EXx }, PREFIX_DATA },
327+ { "%XEvpabsb", { XM, EXx }, PREFIX_DATA },
328+ { "%XEvpabsw", { XM, EXx }, PREFIX_DATA },
329329 { VEX_W_TABLE (EVEX_W_0F381E) },
330330 { VEX_W_TABLE (EVEX_W_0F381F) },
331331 /* 20 */
@@ -359,13 +359,13 @@ static const struct dis386 evex_table[][256] = {
359359 { PREFIX_TABLE (PREFIX_EVEX_0F3838) },
360360 { PREFIX_TABLE (PREFIX_EVEX_0F3839) },
361361 { PREFIX_TABLE (PREFIX_EVEX_0F383A) },
362- { "vpminu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
363- { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
364- { "vpmaxs%DQ", { XM, Vex, EXx }, PREFIX_DATA },
365- { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
366- { "vpmaxu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
362+ { "%XEvpminu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
363+ { "%XEvpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
364+ { "%XEvpmaxs%DQ", { XM, Vex, EXx }, PREFIX_DATA },
365+ { "%XEvpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
366+ { "%XEvpmaxu%DQ", { XM, Vex, EXx }, PREFIX_DATA },
367367 /* 40 */
368- { "vpmull%DQ", { XM, Vex, EXx }, PREFIX_DATA },
368+ { "%XEvpmull%DQ", { XM, Vex, EXx }, PREFIX_DATA },
369369 { Bad_Opcode },
370370 { "vgetexpp%XW", { XM, EXx, EXxEVexS }, PREFIX_DATA },
371371 { "vgetexps%XW", { XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
@@ -461,17 +461,17 @@ static const struct dis386 evex_table[][256] = {
461461 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX }, PREFIX_DATA },
462462 { Bad_Opcode },
463463 { Bad_Opcode },
464- { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
465- { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
464+ { "%XEvfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
465+ { "%XEvfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
466466 /* 98 */
467- { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
468- { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
467+ { "%XEvfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
468+ { "%XEvfmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
469469 { PREFIX_TABLE (PREFIX_EVEX_0F389A) },
470470 { PREFIX_TABLE (PREFIX_EVEX_0F389B) },
471- { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
472- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
473- { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
474- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
471+ { "%XEvfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
472+ { "%XEvfnmadd132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
473+ { "%XEvfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
474+ { "%XEvfnmsub132s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
475475 /* A0 */
476476 { "vpscatterd%DQ", { MVexVSIBDWpX, XM }, PREFIX_DATA },
477477 { "vpscatterq%DQ", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
@@ -479,17 +479,17 @@ static const struct dis386 evex_table[][256] = {
479479 { "vscatterqp%XW", { MVexVSIBQWpX, XMGatherQ }, PREFIX_DATA },
480480 { Bad_Opcode },
481481 { Bad_Opcode },
482- { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
483- { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
482+ { "%XEvfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
483+ { "%XEvfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
484484 /* A8 */
485- { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
486- { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
485+ { "%XEvfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
486+ { "%XEvfmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
487487 { PREFIX_TABLE (PREFIX_EVEX_0F38AA) },
488488 { PREFIX_TABLE (PREFIX_EVEX_0F38AB) },
489- { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
490- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
491- { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
492- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
489+ { "%XEvfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
490+ { "%XEvfnmadd213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
491+ { "%XEvfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
492+ { "%XEvfnmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
493493 /* B0 */
494494 { Bad_Opcode },
495495 { Bad_Opcode },
@@ -497,17 +497,17 @@ static const struct dis386 evex_table[][256] = {
497497 { Bad_Opcode },
498498 { "vpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
499499 { "vpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
500- { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
501- { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
500+ { "%XEvfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
501+ { "%XEvfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
502502 /* B8 */
503- { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
504- { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
505- { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
506- { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
507- { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
508- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
509- { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
510- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
503+ { "%XEvfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
504+ { "%XEvfmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
505+ { "%XEvfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
506+ { "%XEvfmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
507+ { "%XEvfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
508+ { "%XEvfnmadd231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
509+ { "%XEvfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, PREFIX_DATA },
510+ { "%XEvfnmsub231s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, PREFIX_DATA },
511511 /* C0 */
512512 { Bad_Opcode },
513513 { Bad_Opcode },
@@ -540,10 +540,10 @@ static const struct dis386 evex_table[][256] = {
540540 { Bad_Opcode },
541541 { Bad_Opcode },
542542 { Bad_Opcode },
543- { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
544- { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
545- { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
546- { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
543+ { "%XEvaesenc", { XM, Vex, EXx }, PREFIX_DATA },
544+ { "%XEvaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
545+ { "%XEvaesdec", { XM, Vex, EXx }, PREFIX_DATA },
546+ { "%XEvaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
547547 /* E0 */
548548 { Bad_Opcode },
549549 { Bad_Opcode },
@@ -589,7 +589,7 @@ static const struct dis386 evex_table[][256] = {
589589 { Bad_Opcode },
590590 { "valign%DQ", { XM, Vex, EXx, Ib }, PREFIX_DATA },
591591 { VEX_W_TABLE (VEX_W_0F3A04) },
592- { "vpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
592+ { "%XEvpermilp%XD", { XM, EXx, Ib }, PREFIX_DATA },
593593 { Bad_Opcode },
594594 { Bad_Opcode },
595595 /* 08 */
@@ -600,7 +600,7 @@ static const struct dis386 evex_table[][256] = {
600600 { Bad_Opcode },
601601 { Bad_Opcode },
602602 { Bad_Opcode },
603- { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
603+ { "%XEvpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
604604 /* 10 */
605605 { Bad_Opcode },
606606 { Bad_Opcode },
@@ -660,7 +660,7 @@ static const struct dis386 evex_table[][256] = {
660660 { Bad_Opcode },
661661 { VEX_W_TABLE (EVEX_W_0F3A42) },
662662 { EVEX_LEN_TABLE (EVEX_LEN_0F3A43) },
663- { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
663+ { "%XEvpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
664664 { Bad_Opcode },
665665 { Bad_Opcode },
666666 { Bad_Opcode },
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1759,6 +1759,8 @@ struct dis386 {
17591759 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
17601760 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
17611761 "XV" => print "{vex} " pseudo prefix
1762+ "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1763+ is used by an EVEX-encoded (AVX512VL) instruction.
17621764 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
17631765 being false, or no operand at all in 64bit mode, or if suffix_always
17641766 is true.
@@ -3564,71 +3566,71 @@ static const struct dis386 prefix_table[][4] = {
35643566
35653567 /* PREFIX_VEX_0F10 */
35663568 {
3567- { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3568- { "vmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3569- { "vmovupX", { XM, EXEvexXNoBcst }, PREFIX_OPCODE },
3570- { "vmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3569+ { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3570+ { "%XEvmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3571+ { "%XEvmovupX", { XM, EXEvexXNoBcst }, 0 },
3572+ { "%XEvmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
35713573 },
35723574
35733575 /* PREFIX_VEX_0F11 */
35743576 {
3575- { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3576- { "vmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3577- { "vmovupX", { EXxS, XM }, PREFIX_OPCODE },
3578- { "vmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3577+ { "%XEvmovupX", { EXxS, XM }, 0 },
3578+ { "%XEvmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3579+ { "%XEvmovupX", { EXxS, XM }, 0 },
3580+ { "%XEvmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
35793581 },
35803582
35813583 /* PREFIX_VEX_0F12 */
35823584 {
35833585 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3584- { "vmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3586+ { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
35853587 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3586- { "vmov%XDdup", { XM, EXymmq }, 0 },
3588+ { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
35873589 },
35883590
35893591 /* PREFIX_VEX_0F16 */
35903592 {
35913593 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3592- { "vmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3594+ { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
35933595 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
35943596 },
35953597
35963598 /* PREFIX_VEX_0F2A */
35973599 {
35983600 { Bad_Opcode },
3599- { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3601+ { "%XEvcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
36003602 { Bad_Opcode },
3601- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3603+ { "%XEvcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
36023604 },
36033605
36043606 /* PREFIX_VEX_0F2C */
36053607 {
36063608 { Bad_Opcode },
3607- { "vcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3609+ { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
36083610 { Bad_Opcode },
3609- { "vcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3611+ { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
36103612 },
36113613
36123614 /* PREFIX_VEX_0F2D */
36133615 {
36143616 { Bad_Opcode },
3615- { "vcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3617+ { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
36163618 { Bad_Opcode },
3617- { "vcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3619+ { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
36183620 },
36193621
36203622 /* PREFIX_VEX_0F2E */
36213623 {
3622- { "vucomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3624+ { "%XEvucomisX", { XMScalar, EXd, EXxEVexS }, 0 },
36233625 { Bad_Opcode },
3624- { "vucomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3626+ { "%XEvucomisX", { XMScalar, EXq, EXxEVexS }, 0 },
36253627 },
36263628
36273629 /* PREFIX_VEX_0F2F */
36283630 {
3629- { "vcomisX", { XMScalar, EXd, EXxEVexS }, PREFIX_OPCODE },
3631+ { "%XEvcomisX", { XMScalar, EXd, EXxEVexS }, 0 },
36303632 { Bad_Opcode },
3631- { "vcomisX", { XMScalar, EXq, EXxEVexS }, PREFIX_OPCODE },
3633+ { "%XEvcomisX", { XMScalar, EXq, EXxEVexS }, 0 },
36323634 },
36333635
36343636 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
@@ -3743,10 +3745,10 @@ static const struct dis386 prefix_table[][4] = {
37433745
37443746 /* PREFIX_VEX_0F51 */
37453747 {
3746- { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3747- { "vsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3748- { "vsqrtpX", { XM, EXx, EXxEVexR }, PREFIX_OPCODE },
3749- { "vsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3748+ { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3749+ { "%XEvsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3750+ { "%XEvsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3751+ { "%XEvsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
37503752 },
37513753
37523754 /* PREFIX_VEX_0F52 */
@@ -3763,26 +3765,26 @@ static const struct dis386 prefix_table[][4] = {
37633765
37643766 /* PREFIX_VEX_0F58 */
37653767 {
3766- { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3767- { "vadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3768- { "vaddpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3769- { "vadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3768+ { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3769+ { "%XEvadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3770+ { "%XEvaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3771+ { "%XEvadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
37703772 },
37713773
37723774 /* PREFIX_VEX_0F59 */
37733775 {
3774- { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3775- { "vmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3776- { "vmulpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3777- { "vmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3776+ { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3777+ { "%XEvmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3778+ { "%XEvmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3779+ { "%XEvmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
37783780 },
37793781
37803782 /* PREFIX_VEX_0F5A */
37813783 {
3782- { "vcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3783- { "vcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3784- { "vcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3785- { "vcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3784+ { "%XEvcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3785+ { "%XEvcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3786+ { "%XEvcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3787+ { "%XEvcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
37863788 },
37873789
37883790 /* PREFIX_VEX_0F5B */
@@ -3794,34 +3796,34 @@ static const struct dis386 prefix_table[][4] = {
37943796
37953797 /* PREFIX_VEX_0F5C */
37963798 {
3797- { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3798- { "vsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3799- { "vsubpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3800- { "vsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3799+ { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3800+ { "%XEvsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3801+ { "%XEvsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3802+ { "%XEvsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
38013803 },
38023804
38033805 /* PREFIX_VEX_0F5D */
38043806 {
3805- { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3806- { "vmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3807- { "vminpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3808- { "vmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3807+ { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3808+ { "%XEvmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3809+ { "%XEvminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3810+ { "%XEvmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
38093811 },
38103812
38113813 /* PREFIX_VEX_0F5E */
38123814 {
3813- { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3814- { "vdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3815- { "vdivpX", { XM, Vex, EXx, EXxEVexR }, PREFIX_OPCODE },
3816- { "vdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3815+ { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3816+ { "%XEvdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3817+ { "%XEvdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3818+ { "%XEvdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
38173819 },
38183820
38193821 /* PREFIX_VEX_0F5F */
38203822 {
3821- { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3822- { "vmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3823- { "vmaxpX", { XM, Vex, EXx, EXxEVexS }, PREFIX_OPCODE },
3824- { "vmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3823+ { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3824+ { "%XEvmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3825+ { "%XEvmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3826+ { "%XEvmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
38253827 },
38263828
38273829 /* PREFIX_VEX_0F6F */
@@ -6681,32 +6683,32 @@ static const struct dis386 vex_table[][256] = {
66816683 static const struct dis386 vex_len_table[][2] = {
66826684 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
66836685 {
6684- { "vmovlpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6686+ { "%XEvmovlpX", { XM, Vex, EXq }, 0 },
66856687 },
66866688
66876689 /* VEX_LEN_0F12_P_0_M_1 */
66886690 {
6689- { "vmovhlp%XS", { XM, Vex, EXq }, 0 },
6691+ { "%XEvmovhlp%XS", { XM, Vex, EXq }, 0 },
66906692 },
66916693
66926694 /* VEX_LEN_0F13_M_0 */
66936695 {
6694- { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6696+ { "%XEvmovlpX", { EXq, XM }, PREFIX_OPCODE },
66956697 },
66966698
66976699 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
66986700 {
6699- { "vmovhpX", { XM, Vex, EXq }, PREFIX_OPCODE },
6701+ { "%XEvmovhpX", { XM, Vex, EXq }, 0 },
67006702 },
67016703
67026704 /* VEX_LEN_0F16_P_0_M_1 */
67036705 {
6704- { "vmovlhp%XS", { XM, Vex, EXq }, 0 },
6706+ { "%XEvmovlhp%XS", { XM, Vex, EXq }, 0 },
67056707 },
67066708
67076709 /* VEX_LEN_0F17_M_0 */
67086710 {
6709- { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6711+ { "%XEvmovhpX", { EXq, XM }, PREFIX_OPCODE },
67106712 },
67116713
67126714 /* VEX_LEN_0F41 */
@@ -6758,7 +6760,7 @@ static const struct dis386 vex_len_table[][2] = {
67586760
67596761 /* VEX_LEN_0F6E */
67606762 {
6761- { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6763+ { "%XEvmovK", { XMScalar, Edq }, PREFIX_DATA },
67626764 },
67636765
67646766 /* VEX_LEN_0F77 */
@@ -6769,12 +6771,12 @@ static const struct dis386 vex_len_table[][2] = {
67696771
67706772 /* VEX_LEN_0F7E_P_1 */
67716773 {
6772- { "vmovq", { XMScalar, EXq }, 0 },
6774+ { "%XEvmovq", { XMScalar, EXq }, 0 },
67736775 },
67746776
67756777 /* VEX_LEN_0F7E_P_2 */
67766778 {
6777- { "vmovK", { Edq, XMScalar }, 0 },
6779+ { "%XEvmovK", { Edq, XMScalar }, 0 },
67786780 },
67796781
67806782 /* VEX_LEN_0F90 */
@@ -6819,17 +6821,17 @@ static const struct dis386 vex_len_table[][2] = {
68196821
68206822 /* VEX_LEN_0FC4 */
68216823 {
6822- { "vpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
6824+ { "%XEvpinsrw", { XM, Vex, Edw, Ib }, PREFIX_DATA },
68236825 },
68246826
68256827 /* VEX_LEN_0FC5 */
68266828 {
6827- { "vpextrw", { Gd, XS, Ib }, PREFIX_DATA },
6829+ { "%XEvpextrw", { Gd, XS, Ib }, PREFIX_DATA },
68286830 },
68296831
68306832 /* VEX_LEN_0FD6 */
68316833 {
6832- { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6834+ { "%XEvmovq", { EXqS, XMScalar }, PREFIX_DATA },
68336835 },
68346836
68356837 /* VEX_LEN_0FF7 */
@@ -6986,22 +6988,22 @@ static const struct dis386 vex_len_table[][2] = {
69866988
69876989 /* VEX_LEN_0F3A14 */
69886990 {
6989- { "vpextrb", { Edb, XM, Ib }, PREFIX_DATA },
6991+ { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
69906992 },
69916993
69926994 /* VEX_LEN_0F3A15 */
69936995 {
6994- { "vpextrw", { Edw, XM, Ib }, PREFIX_DATA },
6996+ { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
69956997 },
69966998
69976999 /* VEX_LEN_0F3A16 */
69987000 {
6999- { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7001+ { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
70007002 },
70017003
70027004 /* VEX_LEN_0F3A17 */
70037005 {
7004- { "vextractps", { Ed, XM, Ib }, PREFIX_DATA },
7006+ { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
70057007 },
70067008
70077009 /* VEX_LEN_0F3A18 */
@@ -7018,17 +7020,17 @@ static const struct dis386 vex_len_table[][2] = {
70187020
70197021 /* VEX_LEN_0F3A20 */
70207022 {
7021- { "vpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7023+ { "%XEvpinsrb", { XM, Vex, Edb, Ib }, PREFIX_DATA },
70227024 },
70237025
70247026 /* VEX_LEN_0F3A21 */
70257027 {
7026- { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7028+ { "%XEvinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
70277029 },
70287030
70297031 /* VEX_LEN_0F3A22 */
70307032 {
7031- { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7033+ { "%XEvpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
70327034 },
70337035
70347036 /* VEX_LEN_0F3A30 */
@@ -7470,7 +7472,7 @@ static const struct dis386 vex_w_table[][2] = {
74707472 },
74717473 {
74727474 /* VEX_W_0F380C */
7473- { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7475+ { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
74747476 },
74757477 {
74767478 /* VEX_W_0F380D */
@@ -7494,7 +7496,7 @@ static const struct dis386 vex_w_table[][2] = {
74947496 },
74957497 {
74967498 /* VEX_W_0F3818 */
7497- { "vbroadcastss", { XM, EXd }, PREFIX_DATA },
7499+ { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
74987500 },
74997501 {
75007502 /* VEX_W_0F3819_L_1 */
@@ -7570,7 +7572,7 @@ static const struct dis386 vex_w_table[][2] = {
75707572 },
75717573 {
75727574 /* VEX_W_0F3858 */
7573- { "vpbroadcastd", { XM, EXd }, PREFIX_DATA },
7575+ { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
75747576 },
75757577 {
75767578 /* VEX_W_0F3859 */
@@ -7606,25 +7608,25 @@ static const struct dis386 vex_w_table[][2] = {
76067608 },
76077609 {
76087610 /* VEX_W_0F3878 */
7609- { "vpbroadcastb", { XM, EXb }, PREFIX_DATA },
7611+ { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
76107612 },
76117613 {
76127614 /* VEX_W_0F3879 */
7613- { "vpbroadcastw", { XM, EXw }, PREFIX_DATA },
7615+ { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
76147616 },
76157617 {
76167618 /* VEX_W_0F38CF */
7617- { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7619+ { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
76187620 },
76197621 {
76207622 /* VEX_W_0F3A00_L_1 */
76217623 { Bad_Opcode },
7622- { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7624+ { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
76237625 },
76247626 {
76257627 /* VEX_W_0F3A01_L_1 */
76267628 { Bad_Opcode },
7627- { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7629+ { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
76287630 },
76297631 {
76307632 /* VEX_W_0F3A02 */
@@ -7632,7 +7634,7 @@ static const struct dis386 vex_w_table[][2] = {
76327634 },
76337635 {
76347636 /* VEX_W_0F3A04 */
7635- { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7637+ { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
76367638 },
76377639 {
76387640 /* VEX_W_0F3A05 */
@@ -7652,7 +7654,7 @@ static const struct dis386 vex_w_table[][2] = {
76527654 },
76537655 {
76547656 /* VEX_W_0F3A1D */
7655- { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7657+ { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
76567658 },
76577659 {
76587660 /* VEX_W_0F3A38_L_1 */
@@ -7681,12 +7683,12 @@ static const struct dis386 vex_w_table[][2] = {
76817683 {
76827684 /* VEX_W_0F3ACE */
76837685 { Bad_Opcode },
7684- { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7686+ { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
76857687 },
76867688 {
76877689 /* VEX_W_0F3ACF */
76887690 { Bad_Opcode },
7689- { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7691+ { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
76907692 },
76917693 /* VEX_W_0FXOP_08_85_L_0 */
76927694 {
@@ -8218,7 +8220,7 @@ static const struct dis386 mod_table[][2] = {
82188220 },
82198221 {
82208222 /* MOD_VEX_0F2B */
8221- { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8223+ { "%XEvmovntpX", { Mx, XM }, PREFIX_OPCODE },
82228224 },
82238225 {
82248226 /* MOD_VEX_0F41_L_1 */
@@ -10469,7 +10471,41 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
1046910471 else
1047010472 *ins->obufp++ = 'w';
1047110473 break;
10472- case 'E': /* For jcxz/jecxz */
10474+ case 'E':
10475+ if (l == 1)
10476+ {
10477+ switch (last[0])
10478+ {
10479+ case 'X':
10480+ if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10481+ || !ins->vex.r
10482+ || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10483+ || !ins->vex.v || ins->vex.mask_register_specifier)
10484+ break;
10485+ /* AVX512 extends a number of V*D insns to also have V*Q variants,
10486+ merely distinguished by EVEX.W. Look for a use of the
10487+ respective macro. */
10488+ if (ins->vex.w)
10489+ {
10490+ const char *pct = strchr (p + 1, '%');
10491+
10492+ if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10493+ break;
10494+ }
10495+ *ins->obufp++ = '{';
10496+ *ins->obufp++ = 'e';
10497+ *ins->obufp++ = 'v';
10498+ *ins->obufp++ = 'e';
10499+ *ins->obufp++ = 'x';
10500+ *ins->obufp++ = '}';
10501+ *ins->obufp++ = ' ';
10502+ break;
10503+ default:
10504+ abort ();
10505+ }
10506+ break;
10507+ }
10508+ /* For jcxz/jecxz */
1047310509 if (ins->address_mode == mode_64bit)
1047410510 {
1047510511 if (sizeflag & AFLAG)