Revisão | 0e13ba7889432c5e2f1bdb1b25e7076ca1b1dcba (tree) |
---|---|
Hora | 2020-02-22 01:07:03 |
Autor | Richard Henderson <richard.henderson@lina...> |
Commiter | Peter Maydell |
target/arm: Rename isar_feature_aa32_simd_r32
The old name, isar_feature_aa32_fp_d32, does not reflect
the MVFR0 field name, SIMDReg.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200214181547.21408-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: wrapped one long line]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
@@ -3450,7 +3450,7 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) | ||
3450 | 3450 | return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1; |
3451 | 3451 | } |
3452 | 3452 | |
3453 | -static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) | |
3453 | +static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) | |
3454 | 3454 | { |
3455 | 3455 | /* Return true if D16-D31 are implemented */ |
3456 | 3456 | return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2; |
@@ -201,7 +201,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) | ||
201 | 201 | } |
202 | 202 | |
203 | 203 | /* UNDEF accesses to D16-D31 if they don't exist */ |
204 | - if (dp && !dc_isar_feature(aa32_fp_d32, s) && | |
204 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | |
205 | 205 | ((a->vm | a->vn | a->vd) & 0x10)) { |
206 | 206 | return false; |
207 | 207 | } |
@@ -334,7 +334,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) | ||
334 | 334 | } |
335 | 335 | |
336 | 336 | /* UNDEF accesses to D16-D31 if they don't exist */ |
337 | - if (dp && !dc_isar_feature(aa32_fp_d32, s) && | |
337 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | |
338 | 338 | ((a->vm | a->vn | a->vd) & 0x10)) { |
339 | 339 | return false; |
340 | 340 | } |
@@ -420,7 +420,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) | ||
420 | 420 | } |
421 | 421 | |
422 | 422 | /* UNDEF accesses to D16-D31 if they don't exist */ |
423 | - if (dp && !dc_isar_feature(aa32_fp_d32, s) && | |
423 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && | |
424 | 424 | ((a->vm | a->vd) & 0x10)) { |
425 | 425 | return false; |
426 | 426 | } |
@@ -484,7 +484,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
484 | 484 | } |
485 | 485 | |
486 | 486 | /* UNDEF accesses to D16-D31 if they don't exist */ |
487 | - if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
487 | + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
488 | 488 | return false; |
489 | 489 | } |
490 | 490 |
@@ -556,7 +556,7 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) | ||
556 | 556 | uint32_t offset; |
557 | 557 | |
558 | 558 | /* UNDEF accesses to D16-D31 if they don't exist */ |
559 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { | |
559 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { | |
560 | 560 | return false; |
561 | 561 | } |
562 | 562 |
@@ -615,7 +615,7 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) | ||
615 | 615 | uint32_t offset; |
616 | 616 | |
617 | 617 | /* UNDEF accesses to D16-D31 if they don't exist */ |
618 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { | |
618 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { | |
619 | 619 | return false; |
620 | 620 | } |
621 | 621 |
@@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
662 | 662 | } |
663 | 663 | |
664 | 664 | /* UNDEF accesses to D16-D31 if they don't exist */ |
665 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { | |
665 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { | |
666 | 666 | return false; |
667 | 667 | } |
668 | 668 |
@@ -912,7 +912,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a) | ||
912 | 912 | */ |
913 | 913 | |
914 | 914 | /* UNDEF accesses to D16-D31 if they don't exist */ |
915 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
915 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
916 | 916 | return false; |
917 | 917 | } |
918 | 918 |
@@ -978,7 +978,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) | ||
978 | 978 | TCGv_i64 tmp; |
979 | 979 | |
980 | 980 | /* UNDEF accesses to D16-D31 if they don't exist */ |
981 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { | |
981 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | |
982 | 982 | return false; |
983 | 983 | } |
984 | 984 |
@@ -1101,7 +1101,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) | ||
1101 | 1101 | } |
1102 | 1102 | |
1103 | 1103 | /* UNDEF accesses to D16-D31 if they don't exist */ |
1104 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) { | |
1104 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { | |
1105 | 1105 | return false; |
1106 | 1106 | } |
1107 | 1107 |
@@ -1309,7 +1309,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn, | ||
1309 | 1309 | TCGv_ptr fpst; |
1310 | 1310 | |
1311 | 1311 | /* UNDEF accesses to D16-D31 if they don't exist */ |
1312 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) { | |
1312 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { | |
1313 | 1313 | return false; |
1314 | 1314 | } |
1315 | 1315 |
@@ -1458,7 +1458,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm) | ||
1458 | 1458 | TCGv_i64 f0, fd; |
1459 | 1459 | |
1460 | 1460 | /* UNDEF accesses to D16-D31 if they don't exist */ |
1461 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) { | |
1461 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { | |
1462 | 1462 | return false; |
1463 | 1463 | } |
1464 | 1464 |
@@ -1822,7 +1822,8 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) | ||
1822 | 1822 | } |
1823 | 1823 | |
1824 | 1824 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
1825 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x10)) { | |
1825 | + if (!dc_isar_feature(aa32_simd_r32, s) && | |
1826 | + ((a->vd | a->vn | a->vm) & 0x10)) { | |
1826 | 1827 | return false; |
1827 | 1828 | } |
1828 | 1829 |
@@ -1921,7 +1922,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) | ||
1921 | 1922 | vd = a->vd; |
1922 | 1923 | |
1923 | 1924 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
1924 | - if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) { | |
1925 | + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { | |
1925 | 1926 | return false; |
1926 | 1927 | } |
1927 | 1928 |
@@ -2065,7 +2066,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a) | ||
2065 | 2066 | } |
2066 | 2067 | |
2067 | 2068 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2068 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { | |
2069 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { | |
2069 | 2070 | return false; |
2070 | 2071 | } |
2071 | 2072 |
@@ -2138,7 +2139,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a) | ||
2138 | 2139 | } |
2139 | 2140 | |
2140 | 2141 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2141 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { | |
2142 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | |
2142 | 2143 | return false; |
2143 | 2144 | } |
2144 | 2145 |
@@ -2204,7 +2205,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a) | ||
2204 | 2205 | } |
2205 | 2206 | |
2206 | 2207 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2207 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
2208 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
2208 | 2209 | return false; |
2209 | 2210 | } |
2210 | 2211 |
@@ -2264,7 +2265,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a) | ||
2264 | 2265 | } |
2265 | 2266 | |
2266 | 2267 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2267 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { | |
2268 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { | |
2268 | 2269 | return false; |
2269 | 2270 | } |
2270 | 2271 |
@@ -2325,7 +2326,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a) | ||
2325 | 2326 | } |
2326 | 2327 | |
2327 | 2328 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2328 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { | |
2329 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { | |
2329 | 2330 | return false; |
2330 | 2331 | } |
2331 | 2332 |
@@ -2384,7 +2385,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a) | ||
2384 | 2385 | } |
2385 | 2386 | |
2386 | 2387 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2387 | - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { | |
2388 | + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { | |
2388 | 2389 | return false; |
2389 | 2390 | } |
2390 | 2391 |
@@ -2412,7 +2413,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a) | ||
2412 | 2413 | TCGv_i32 vm; |
2413 | 2414 | |
2414 | 2415 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2415 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { | |
2416 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | |
2416 | 2417 | return false; |
2417 | 2418 | } |
2418 | 2419 |
@@ -2440,7 +2441,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a) | ||
2440 | 2441 | TCGv_i32 vd; |
2441 | 2442 | |
2442 | 2443 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2443 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
2444 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
2444 | 2445 | return false; |
2445 | 2446 | } |
2446 | 2447 |
@@ -2494,7 +2495,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a) | ||
2494 | 2495 | TCGv_ptr fpst; |
2495 | 2496 | |
2496 | 2497 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2497 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { | |
2498 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | |
2498 | 2499 | return false; |
2499 | 2500 | } |
2500 | 2501 |
@@ -2534,7 +2535,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) | ||
2534 | 2535 | } |
2535 | 2536 | |
2536 | 2537 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2537 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
2538 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
2538 | 2539 | return false; |
2539 | 2540 | } |
2540 | 2541 |
@@ -2627,7 +2628,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a) | ||
2627 | 2628 | } |
2628 | 2629 | |
2629 | 2630 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2630 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { | |
2631 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { | |
2631 | 2632 | return false; |
2632 | 2633 | } |
2633 | 2634 |
@@ -2723,7 +2724,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a) | ||
2723 | 2724 | TCGv_ptr fpst; |
2724 | 2725 | |
2725 | 2726 | /* UNDEF accesses to D16-D31 if they don't exist. */ |
2726 | - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { | |
2727 | + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { | |
2727 | 2728 | return false; |
2728 | 2729 | } |
2729 | 2730 |