Revisão | 368bec88d1916f65050be305f88c10a46075a51c (tree) |
---|---|
Hora | 2019-02-22 03:16:19 |
Autor | Sven Schnelle <svens@stac...> |
Commiter | Richard Henderson |
hw/hppa/dino: mask out lower 2 bits of PCI config addr
some versions of HP-UX 10.20 seems to rely on the fact that DINO
strips out the lower 2 bits of the PCI configuration address.
Also update the binary SeaBIOS distributed to the latest version
from Helge's repository, which is required with that change.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Message-Id: <20190218183314.20157-1-svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
@@ -178,7 +178,7 @@ static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, | ||
178 | 178 | case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: |
179 | 179 | /* Read from PCI IO space. */ |
180 | 180 | io = &address_space_io; |
181 | - ioaddr = s->parent_obj.config_reg; | |
181 | + ioaddr = s->parent_obj.config_reg + (addr & 3); | |
182 | 182 | switch (size) { |
183 | 183 | case 1: |
184 | 184 | val = address_space_ldub(io, ioaddr, attrs, &ret); |
@@ -250,7 +250,7 @@ static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, | ||
250 | 250 | case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: |
251 | 251 | /* Write into PCI IO space. */ |
252 | 252 | io = &address_space_io; |
253 | - ioaddr = s->parent_obj.config_reg; | |
253 | + ioaddr = s->parent_obj.config_reg + (addr & 3); | |
254 | 254 | switch (size) { |
255 | 255 | case 1: |
256 | 256 | address_space_stb(io, ioaddr, val, attrs, &ret); |
@@ -360,6 +360,27 @@ static const MemoryRegionOps dino_config_data_ops = { | ||
360 | 360 | .endianness = DEVICE_LITTLE_ENDIAN, |
361 | 361 | }; |
362 | 362 | |
363 | +static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len) | |
364 | +{ | |
365 | + PCIHostState *s = opaque; | |
366 | + return s->config_reg; | |
367 | +} | |
368 | + | |
369 | +static void dino_config_addr_write(void *opaque, hwaddr addr, | |
370 | + uint64_t val, unsigned len) | |
371 | +{ | |
372 | + PCIHostState *s = opaque; | |
373 | + s->config_reg = val & ~3U; | |
374 | +} | |
375 | + | |
376 | +static const MemoryRegionOps dino_config_addr_ops = { | |
377 | + .read = dino_config_addr_read, | |
378 | + .write = dino_config_addr_write, | |
379 | + .valid.min_access_size = 4, | |
380 | + .valid.max_access_size = 4, | |
381 | + .endianness = DEVICE_BIG_ENDIAN, | |
382 | +}; | |
383 | + | |
363 | 384 | static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, |
364 | 385 | int devfn) |
365 | 386 | { |
@@ -440,7 +461,7 @@ PCIBus *dino_init(MemoryRegion *addr_space, | ||
440 | 461 | |
441 | 462 | /* Dino PCI config. */ |
442 | 463 | memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), |
443 | - &pci_host_conf_be_ops, dev, "pci-conf-idx", 4); | |
464 | + &dino_config_addr_ops, dev, "pci-conf-idx", 4); | |
444 | 465 | memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), |
445 | 466 | &dino_config_data_ops, dev, "pci-conf-data", 4); |
446 | 467 | memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, |