Commit: 71f07731488e9ade674ee396208317ab2db3cce1 - uboot (git)

Commit MetaInfo

• Revisão: 71f07731488e9ade674ee396208317ab2db3cce1 (tree)
• Hora: 2022-07-26 15:23:54
• Autor: Ashok Reddy Soma <ashok.reddy.soma@xili...>
• Commiter: Michal Simek

Mensagem de Log

mmc: zynq_sdhci: Fix timing macros for MMC High speed

Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.

Signed-off-by: Ashok Reddy Soma <[e-mail]>
Link: https://lore.kernel.org/r/[e-mail]
Signed-off-by: Michal Simek <[e-mail]>

Mudança Sumário

• modified: drivers/mmc/zynq_sdhci.c

Diff

--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -101,8 +101,8 @@ static const u8 mode2timing[] = {
 	[MMC_LEGACY] = MMC_TIMING_LEGACY,
 	[MMC_HS] = MMC_TIMING_MMC_HS,
 	[SD_HS] = MMC_TIMING_SD_HS,
-	[MMC_HS_52] = MMC_TIMING_UHS_SDR50,
-	[MMC_DDR_52] = MMC_TIMING_UHS_DDR50,
+	[MMC_HS_52] = MMC_TIMING_MMC_HS,
+	[MMC_DDR_52] = MMC_TIMING_MMC_DDR52,
 	[UHS_SDR12] = MMC_TIMING_UHS_SDR12,
 	[UHS_SDR25] = MMC_TIMING_UHS_SDR25,
 	[UHS_SDR50] = MMC_TIMING_UHS_SDR50,