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Projeto Descrição

GPL Cver is a full Verilog HDL IEEE P1364 standard
simulator. It is a high capacity commercial
quality interpretive Verilog simulator. Full
support for all three PLI interfaces is included:
tf_, acc_, and vpi_. Some Verilog 2001 features
are supported.

System Requirements

System requirement is not defined
Information regarding Project Releases and Project Resources. Note that the information here is a quote from Freecode.com page, and the downloads themselves may not be hosted on OSDN.

2004-03-03 20:41
1.10g

Existe agora um makefile para Cygwin, PLI e funciona com Cygwin liberação 1,55 e versões anteriores. O código do parâmetro foi reescrito para corresponder XL para ambos libra e tpConstraints.
Tags: Minor bugfixes
There is now a makefile for Cygwin, and PLI works with Cygwin release 1.55 and earlier. The parameter code has been rewritten to match XL for both pound and defparams.

2004-01-30 19:13
1.10f

Esta é uma outra versão de correções menores.
Tags: Minor bugfixes
This is another minor bugfix release.

2003-12-19 22:51
1.10d

Tags: Minor bugfixes

2003-09-20 10:05
1.10b

Esta versão corrige um bug na gravação de mudança que causou extra incorreta $ monitor, e um problema com zero repetir largura concatenar expressões constantes.
Tags: Minor bugfixes
This version fixes a bug in the change recording that
caused extra incorrect $monitor, and a problem with zero
width concatenate repeat constant expressions.

2003-08-14 03:55
1.10

Tags: Initial freshmeat announcement

Project Resources